Abstract: A method and signal therfor embodied in a carrier wave for sending information from transmit stations to receive stations over a transmission medium of a frame-based communications network. The information is sent in transmit frames having a frame format comprising a fixed rate header, followed by a variable rate payload, followed by a fixed rate trailer. The fixed rate header includes a preamble. The preamble has a repetition of four symbol sequences for facilitating power estimation, gain control, baud frequency offset estimation, equalizer training, carrier sensing and collision detection. The preamble also includes a frame control field.

Abstract: A digital television signal is intercepted by a plurality of antennas to produce a corresponding plurality of input signals. The antennas have different directionality so they can be combined in a way that reduces multipath echoes. In one embodiment, the antennas are arranged to operate in a diversity or scanned array mode. In another embodiment, the antennas are arranged to operate in a adaptive phased array mode. The input signals intercepted by the antenna are subjected to vestigial sideband (VSB) processing to produce a single VSB processed signal, which is decoded to form a display drive signal. A plurality of input signals in a VSB receiver having a plurality of antennas with different directionality are evaluated to determine how the input signals should be combined to reduce multipath echoes.

Abstract: An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

Abstract: According to the present invention, the bandwidth of a TDD channel is increased where multiple slave devices communicate with a master device over the channel. According to an aspect of the present invention, the master device can increase channel bandwidth by utilizing available transmit slots that occur during receipt of a multi-slot packet from a slave device. For example, the master device receives a first packet at a first frequency from a first slave via the channel. The master determines whether the first packet is a multi-slot packet, and if so, transmits a second packet to a second slave via the channel at a second frequency different from the first frequency. The second packet is transmitted after receipt of the first packet, but prior to the end of the first packet.

Abstract: A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port Serdes transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.

Abstract: Driver circuits of the present invention provide current to drive laser diodes. The output current of the driver circuit includes a data signal and a low frequency tone signal. The low frequency tone signal is within the bandwidth of a power control feedback loop. The tone signal introduces low frequency noise into the output signal of the driver circuit. The low frequency noise causes jitter at the zero crossing points of the driver circuit output signal. A laser driver circuit of the present invention provides a compensation current to a laser diode. The compensation current is out of phase with the tone signal. The compensation current eliminates the low frequency noise in the output signal of the laser driver circuit.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.

Abstract: A printed dipole antenna includes a metal trace having first type sections and second type sections, wherein currents within the first type sections substantially cancel and currents the second type sections are substantially cumulative.

Abstract: A communication unit (30) arranged to send transmit data includes a receiver (32) arranged to recover input data transmitted at a downstream transfer rate in response to a symbol clock (20) signal. A transmitter (40) is arranged to transmit the transmit data at an upstream transfer rate in response to an upstream transmit clock signal (TX_CLKA) that is coordinated with the symbol clock signal. The frequency or repetition rate of the upstream transmit clock signal is defined at least in part by a predetermined relationship between the downstream transfer rate and the upstream transfer rate, such as a ratio of the downstream transfer rate and the upstream transfer rate.

Abstract: A decoder providing asynchronous reset, redundancy, or both. an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel.

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage.

Abstract: Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a selectable bias responsive to the comparison. By combining a portion of the input signal with the selectable bias, a reduced precision signal, having minimized or eliminated rounding error, is generated. The selectable bias corresponds to a predetermined characteristic of one of bias, an error signal, the input datum, the reduced precision datum, and a combination thereof.

Abstract: A network device having a plurality of ports including address resolution logic (ARL), a first switch, a second switch, and a CPU. The first and second switches include groups of ports which are a subset of the plurality of ports and are numbered by different numbering schemes, rate control logic for performing rate control functions related to switching data packets between the network ports, and local communications channels for transmitting messages between the groups of ports and the rate control logic. The first switch is configured to generate a rate control message and relay the rate control message to the second switch, and a first link port of the first switch is configured to generate a second rate control message based on the first rate control message, relay the second rate control message to the second switch, where the second rate control message is different than the first message.

Abstract: A system and method for detecting and removing tones from an incoming communications channel that may also carry other signals such as, for example, voice is disclosed which includes pre-detecting tones in a communication signal, processing the communication signal to invalidate the tones in response to the tone pre-detection, forwarding the processed communication signal across a network, validating the tone and forwarding tone-on signals across the network in response to the validation.

Abstract: An integrated circuit chip having programmable functions and features in which one-time programmable (OTP) memories are used to implement a non-volatile memory function, and a method for providing the same. The OTP memories may be based on poly-fuses as well as gate-oxide fuses. Because OTP memories are small, less die area is utilized as compared to metal fuses. Addtionally, because OTP memories can be implemented as part of standard complementary metal oxide semiconductor (CMOS) processes, the method is less costly and complex than the use of electrically-erasable programmable read-only memories (E2PROMs).

Abstract: A differential preamplifier includes an active load with adjustable common-mode output level. The active load includes a transistor pair, a resistor pair, and a current source. The transistor load is employed to provide high gain, low offset, and a large bandwidth for the differential preamplifier. The resistor pair and current source are used to increase the common-mode output level of the differential preamplifier and to bias the transistor load. The current source can be varied to provide an adjustable common-mode output level suitable for driving next stage devices. The active load design allows the differential preamplifier to operate using only low power voltage supplies and with small-sized transistors.

Abstract: A method can allow a system to selectively control increasing of a bias source in a reference buffer or decreasing impedance looking into a output of the reference buffer for a temporary or selective time period, which can result in an increased overall efficiency of the system. The method can include at least the following steps. A first input signal is received at an input of a reference buffer. A second input signal is received from a load at an output of the reference buffer. A value of a bias source coupled to the output of the reference buffer is modulated, such that a spike of a signal at the output of the reference buffer caused by the second input signal is maintained below a threshold value. Alternatively, an impedance looking into the output of the reference buffer is modulated, such that a spike of a signal at the output of the reference buffer caused by the second input signal is maintained below a threshold value.

Abstract: A method and apparatus for providing improved security and improved roaming transition times in wireless networks. In the present invention, the same pairwise master key (PMK) from an authentication server can be used across multiple access points and a new pairwise transition key (PTK) is derived for each association of a station to any of the access points. A plurality of access points are organized in functional hierarchical levels and are operable to advertise an indicator of the PMK cache depth supported by a group of access points (N) and an ordered list of the identifiers for the derivation path. Access points in each level in the cache hierarchy compute the derived pairwise master keys (DPMKs) for devices in the next lower level in the hierarchy and then deliver the DPMKs to those devices. An access point calculates the PTK as part of the security exchange process when the station wishes to associate to the access point. The station also computes the PTK as part of the security exchange process.

Abstract: Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of the present invention attempt to maintain the proper current ratio between reference and output supplies by adjusting the reference output of the current mirror. An existing reference voltage on the output side of the mirror can be used or a reference voltage can be created to be used for the voltage regulation of the reference side of the current mirror.