Abstract: A Radio Frequency RF transmitter includes a translational loop architecture that supports non-constant envelope modulation types and includes by adjusting the envelope of the translational loop at the translational loop output. The RF transmitter includes a phase equalizer, an Intermediate Frequency (IF) modulator, a translational loop, an envelope time delay adjust block, an envelope adjust block, and a time delay calibration block. The phase equalizer receives a modulated baseband signal and phase equalizes the modulated baseband signal to produce a phase equalized modulated baseband signal. The IF modulator receives the phase equalized modulated baseband signal and produces a modulated IF signal having a non-constant envelope. The translational loop receives the modulated IF signal and produces a modulated RF signal having a constant envelope.

Abstract: A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having undesired frequency tones is divided into even and odd data sub-sequences. Each of the sub-sequences is processed by a dynamic element matching encoder, with a transfer function H(z?1). The resulting processed sub-sequences are combined into an output sequence. The undesired frequency tones are substantially reduced in the output sequence.

Abstract: The accuracy of output power in a digital-to-analog converter (DAC) is critical in certain applications. When bi-CMOS technology is used to implement a DAC, a number of factors affect the gain accuracy of the DAC. The present invention provides a circuit architecture to reduce the variation in these factors to ensure the accuracy of the output power of a DAC. The architecture comprises a bandgap portion, replica circuit and a DAC. The bandgap portion of the architecture provides a constant voltage, while the replica circuit provide a correct current to drive the DAC.

Abstract: A system and method for executing previously created run time executables in a configurable processing element array is disclosed. In one embodiment, this system and method begins by identifying at least one subset of program code. The method may then generate at least one set of configuration memory contexts that replaces each of the at least one subsets of program code, the at least one set of configuration memory contexts emulating the at least one subset of program code. The method may then manipulate the at least one set of multiple context processing elements using the at least one set of configuration memory contexts. The method may then execute the plurality of threads of program code using the at least one set of multiple context processing elements.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A technique has been developed whereby an adaptive receiver may employ decision updating in a manner insensitive to RBS. One realization achieves nearly-ideal training of an adaptive equalizer of a modem during TRN1d training despite potential RBS in a digital portion of the PSTN. Updates in the exemplary realization are based upon the true value of the corresponding equalizer output (the decision) and insensitive to RBS. Adaptive equalizer realizations improve equalizer training by treating the received signal as a sequence of blocks of 24 symbols with 24 corresponding separate decision values. In an exemplary variation, equalizer training begins using a single pair of decision points for coefficient updating. After gross convergence of the equalizer coefficients is achieved the update broadens to include updating each of 24 decision points and the equalizer coefficients.

Abstract: A circuit is provided for controlling the gain of an amplifier, such as an amplifier that may be used in telecommunication devices. The circuit includes an analog portion that receives signals from one or more mixers and that produces an output that is an inverse logarithmic function of the input signal. The output signal is digitally processed by a digital portion of the circuit, which determines whether gain of the amplifier should be increased, decreased, or held constant. Also, methods are provided for controlling the gain of an amplifier.

Abstract: A network switch includes a data port for communicating with a data network, and a statistics counter coupled to the data port for monitoring operational parameters associated with the data port. The statistics counter includes statistics registers therein. A statistics gathering circuit is connected to the statistics counter for reading the statistics registers, and for transmitting the data from the statistics registers to a remote system memory. A method of monitoring port activity in the network switch includes storing port activity data in a statistics register on a network switch, then reading the port activity data with the statistics gathering circuit. The port activity data is transmitted directly to the remote system memory, thereby reconstructing the statistics register in the remote system memory. The remote system memory can then be accessed via a remote CPU to read the reconstructed statistics register.

Abstract: A method and system are disclosed for balancing a plurality of flip-flops across a number of global scan chains in a design of a digital integrated circuit chip. The design of the chip is organized into a number of discrete blocks such that each of the discrete blocks comprises a plurality of flip-flops. Within each discrete block, the plurality of flip-flops is connected to form a number of sub-chains of flip-flops. The sub-chains are then connected, within and across the discrete blocks, to generate a number of global scan chains such that the resultant number of flip-flops in each global scan chain is substantially the same.

Abstract: A Digital-to-Analog-Converter (DAC) includes an interpolation filter, a modulator, and a time dither clock reduction circuit. The interpolation filter receives the digital data and interpolates and filters the digital data to produce an interpolated and filtered digital signal. The modulator receives the interpolated and filtered digital signal and a feedback signal. The modulator modulates the interpolated and filtered digital signal based upon the feedback signal to produce a modulated signal at a modulator clock rate. The time dither clock reduction circuit receives the modulated signal and applies both clock reduction and time dithering to the modulated signal to produce a time dithered/clock reduced modulated signal. The time dithered/clock reduced modulated signal serves as the analog signal and also serves as the feedback signal.

Abstract: A memory-efficient convolutional interleaver/de-interleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: Efficient design to calculate extrinsic information for Soft-In-Soft-Out (SISO) decoder. A design provides for very efficient performing extrinsic value calculation when performing iterative decoding. The design also accommodates a variety of rate controls each having varying bandwidth efficiencies. By grouping and capitalizing on the commonality of many of the intermediate terms that are employed when calculating the extrinsic values needed to perform iterative decoding, a great saving in terms of hardware may be achieved. In addition, this also provides a great deal of improvement in terms of operational speed and overall decoder system efficiency. The design is also adaptable to assist in performing decoding input symbols having multiple bits; a single design may be employed to accommodate different input symbols that have different numbers of bits. The extrinsic calculation employs min* processing in one embodiment; however, the design may also be performed using max*, min, or max processing.

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.

Abstract: A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband processor, and an equalizer module. The RF from end is operable to receive the plurality of received RF bursts and to convert the RF bursts to corresponding baseband signals. The baseband processor operably couples to the RF front end, is operable to receive the baseband signals, is operable to pre-equalization process the baseband signals to produce processed baseband signals, and is operable to post-equalization process soft decisions. The equalizer module operably couples to the baseband processor and is operable to equalize the processed baseband signals to produce the soft decisions. These RF bursts may be contained in adjacent slots or, in non-adjacent slots, or in a combination of adjacent slots and non-adjacent slots.

Abstract: Optimal Decision Feedback Equalizer (DFE) coefficients are determined from a channel estimate h by casting the DFE coefficient problem as a standard recursive least squares (RLS) problem, e.g., the Kalman gain solution to the RLS problem. A fast recursive method, e.g., fast transversal filter (FTF) technique, for computing the Kalman gain is then directly used to compute Feed Forward Equalizer (FFE) coefficients gopt. The complexity of a conventional FTF algorithm is reduced to one third of its original complexity by choosing the length of a Feed Back Equalizer (FBE) coefficients bopt (of the DFE) to force the FTF algorithm to use a lower triangular matrix. The FBE coefficients bopt are then computed by convolving the FFE coefficients gopt with the channel impulse response h. In performing this operation, a convolution matrix that characterizes the channel impulse response h extended to a bigger circulant matrix.

Abstract: A circuit for detecting asynchronous events includes a first event detection latch; and a second event detection latch coupled to the first event detection latch, wherein the first event detection latch is ready to detect an event when the second event detection latch is being reset and wherein the second event detection latch is ready to detect a next event when the first event detection latch is being reset.

Abstract: Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.

Abstract: A system may include at least a first agent and a second agent, and the first agent may be coupled to receive a block signal generated by the second agent. The block signal is indicative of whether or not the second agent is capable of participating in transactions. The first agent initiates or inhibits initiation of a transaction for which the second agent is a participant responsive to the block signal. The system may include additional agents, each configured to generate independent block signals. Other implementations may share block signals among two or more agents. For example, a memory block signal indicative of memory transactions being blocked or not blocked and an input/output (I/O) block signal indicative of I/O transactions being blocked or not blocked may be employed. In yet another implementation, a first agent may provide separate block signals to other agents.

Abstract: A method for exploiting location information inherent in the location of points within a transmitted signal constellation. A common method for assigning weights to branch metrics in a Viterbi decoder is to assign Hamming weights which are summations of the number of places in which a received bit pattern differs from the bit pattern assigned to a branch metric. Signal strength information may be incorporated into the weight assigned to a branch metric in the Viterbi decoder. Additionally information-inherent in the location of the points within a constellation may be taken into account. Bit errors which require a larger deviation to occur are given higher weights, and bit errors which require less deviation to occur are given lower weights. By taking into account signal strength and location information up to 2 dB of coding gain can be realized.