Abstract: Communication processing paths include distortions, such as DC offset in the baseband analog path, local oscillator feed-through distortion, and nonlinearity of gm's and power amplifiers which are calibrated for, separately or in combination. The cascaded DC offset and nonlinear distortions are modeled separately or in combination using even-and-odd order polynomials. A loopback path from the output of one or more distortion causing devices passes through a measurement and calculation module. The calculation module calculates predistortion polynomial's coefficients which will be stored in a look-up table to be used by a baseband predistorter to calibrate the path. The look-up table is stored locally or remotely.

Abstract: A media player is utilized to determine presence of defects in storage devices, and to retrieve replacement data from media management servers. The retrieval of the replacement data is performed during playback and/or use of the storage devices. The replacement data is only utilized during real time playback of the storage devices. The replacement data can also be stored within the data storage player, into the storage devices, and/or into external storage devices accessible during playback operations. Addressing information is created and/or modified to enable use of stored replacement data. A new copy of the data can be created in the same or in new storage device. The media management server performs access authentication operations during replacement data retrieval. The media management server is accessed via user-based webpage-like interfaces and/or dedicated APIs.

Abstract: A power amplifier includes generation, tracking and usage of an envelope of an input RF signal. To improve upon the efficiency of the power amplifier, various configurations include using the tracked envelope, for example, an OFDM signal, to improve the average efficiency. Suitable hardware/software in the form of circuitry, logic gates, and/or code functions to generate and track an envelope of an input RF signal and modulate one or more of the input supply voltage, cascode gate bias or parallel PA branches using the tracked envelope.

Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Abstract: An RF receiver and an RF transmitter, which are integrated in a single substrate, are operable to share a single reconfigurable filter to perform RF receiver filtering and RF transmitter filtering. The reconfigurable filter is configured to operate as a bandpass filter such as an image rejection bandpass filter for receiving RF signals by the RF receiver. The reconfigurable filter operates as a low pass filter for transmitting RF signals by the RF transmitter. The reconfigurable filter is configured to operate in a RF receiver filtering mode or a RF transmitter filtering mode, respectively. The reconfigurable filter is enabled to share configurable circuit components of the radio transceiver in both the radio frequency receiver filtering mode and the radio frequency transmitter filtering mode. The reconfigurable filter transitions between the radio frequency receiver filtering mode and the radio frequency transmitter filtering mode via reconfiguring the shared configurable circuit components.

Abstract: Cellular processors are cascaded to provide different configurations, which result in higher-capacity base stations, increased numbers of simultaneous users over one frequency band, and/or aggregation of several carriers while still using only one radio frequency (RF) chipset. The processors are aligned in both time and frequency, with each processor having a data port that allows data exchange with the other processors. The data alignment and exchange allow the processors, in the aggregate, to act as a single unit, resulting in a scalable architecture that can accommodate different system configurations.

Abstract: A video processing device can determine whether an input pixel includes a keyed video parameter prior to filtering the input pixel. A non-keyed substitute pixel can be generated for the input pixel that includes the keyed video parameter. The non-keyed substitute pixel can be filtered if the input pixel included the keyed video parameter, otherwise the input pixel can be filtered.

Abstract: Aspects of a method and system for determining a limited soft buffer size on transport blocks for rate matching are provided. A data stream may be processed for transmission between a base station (eNodeB) and a UE via HARQ procedures. A two-stage rate-matching algorithm may be used in the HARQ procedures. A limited virtual soft buffer size at the UE in the two-stage rate-matching algorithm may be calculated on site based on channel condition information, available channel bandwidth, number of layers in spatial multiplexing, and the capacity of the UE, respectively. The data stream may be first rate-matched to the calculated limited soft buffer size available at the UE, and forwarded for second stage rate-matching to an actual physical channel size determined by the base station. The amount of bits forwarded for second stage rate-matching may equal to the calculated limited virtual soft buffer size of the virtual soft buffer.

Abstract: The present invention is an integrated cable modem tuner. In one embodiment, the upstream path and the downstream path are integrated on a common semiconductor substrate. The down-stream path can include a TV tuner and digital receiver portion that is integrated on a common semiconductor substrate with the power amplifier of the upstream path. In another embodiment, the TV tuner is implemented on a first semiconductor substrate and the digital receiver portion and the power amplifier are configured on a second semiconductor substrate. However, the two substrates are mounted on a common carrier so that the cable modem appears to be a single chip configuration to the user.

Abstract: Aspects of a method and system for a low-noise, highly-linear receiver front-end are provided. In this regard, a received signal may be processed via one or more transconductances, one or more transimpedance amplifiers (TIAs), and one or more mixers to generate a first baseband signal corresponding to a voltage at a node of the receiver, and a second baseband signal corresponding to a current at the node of the receiver. The first signal and the second signal may be processed to recover information from the received signal. The first signal may be generated via a first one or more signal paths of the receiver and the second signal may be generated via a second one or more signal paths of the receiver.

Abstract: An example of a method of policing a flow in a home network such as a MoCA network may include calculating a policing period, calculating a first credit parameter, initializing a first usage variable at a beginning of the policing period, receiving a packet at an ingress node, calculating the first usage variable based on a first formula, determining whether the first usage variable is less than or equal to the first credit parameter, and making a reservation request when the first usage variable is less than or equal to the first credit parameter. The reservation request is different from an opportunistic reservation request. Examples of a system and a computer program product having instructions stored in a tangible computer-readable storage medium are also provided.

Abstract: Certain aspects of a method and system for speed negotiation for twisted pair links in fibre channel systems are disclosed. Aspects of a method may include communicating data between fibre channel host devices communicatively coupled via a twisted pair link based on a common speed negotiated between the fibre channel host devices. At least one available speed may be determined for the communication of data between the fibre channel host devices over the twisted pair link. The determined available speeds for each of the fibre channel host devices may be exchanged via at least one fast link pulse signal. The common speed negotiated may be a highest available speed for the communication of data between the fibre channel host devices.

Abstract: A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards.

Abstract: Various configurations and arrangements of various communication devices are disclosed. Various integrated circuits that form these communication devices can be fabricated onto one or more semiconductor substrates, chips, and/or dies using a high voltage semiconductor process, a low voltage semiconductor process, or any combination thereof. Some of these high voltage and/or low voltage semiconductor process integrated circuits can be fabricated along with other high voltage and/or low voltage semiconductor process integrated circuits of other modules onto a single semiconductor substrate, chip, and/or die. This allows the low voltage semiconductor process integrated circuits and/or high voltage semiconductor process integrated circuits of one module to be combined with low voltage semiconductor process integrated circuits and/or high voltage semiconductor process integrated circuits of another module of the communication device.

Abstract: A system, method and computer program product is provided for selectively caching domain name system (DNS) information on a network gateway. A CPE attached to the network gateway executes an application that searches files in CPE memory to identify frequently accessed domain names. The domain names are used to generate DNS queries that are transmitted by a network gateway to an IP network for resolution. DNS responses are received from the IP network and parsed to extract each resolved domain name and corresponding IP address, which are then stored in a cache on the network gateway. The cache is then used to resolve DNS queries generated by application programs running on the attached CPE.

Abstract: A method and system for Bluetooth® and Wireless LAN coexistence may include controlling wireless local area network (WLAN) communication and Bluetooth® communication in a coexistence system that handles at least a WLAN communication protocol and a Bluetooth® communication protocol based on time division multiplexing (TDM) and adaptive frequency hopping (AFH). Switching may occur between the WLAN communication and the Bluetooth® communication based on the TDM and the AFH. In one embodiment of the invention, the switching may occur adaptively. Notwithstanding, in instances where it may be determined that AFH is disabled, switching to TDM may occur. WLAN communication and/or Bluetooth® communication may be disabled or enabled based on a state of at the WLAN communication and/or the Bluetooth® communication. Use of the AFH may be enabled or disabled based on a link status of the WLAN communication and/or the Bluetooth® communication.

Abstract: Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (?) values and check edge message (?) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.

Abstract: A method and system for optimizing data throughput in a Bluetooth communication system is provided. The method may include determining the bit error rate (BER) of a first Bluetooth packet type of a plurality of Bluetooth packet types transmitted at a first power output level by a Bluetooth transmitter and selecting a second packet type from the plurality of Bluetooth packet types in response to determining the bit error rate. The different packet types may comprise DM1, DM3, DM5, DH1, DH3, DH5, HV1, HV2, HV3, 2DH1, 2DH3, 2DH5, 3DH1, 3DH3, and 3DH5 Bluetooth packets. The method may also include estimating the BER from the packet error rate (PER) of the first Bluetooth packet type, where the PER may be computed by comparing a number of packets of said first Bluetooth packet type with good CRCs to a number of packets of said first Bluetooth packet type with bad CRCs.

Abstract: A power-line communications (PLC) device communicates with a second PLC device via a PLC medium and includes a transmitter and a receiver. The transmitter transmits a Request to Send (RTS) communication to the second PLC device at a first power level. The receiver receives a Clear to Send (CTS) communication from the second PLC device. The transmitter transmits data to the second PLC device at a second power level that is less than the first power level. The transmitter transmits a TDM frame to the second PLC device that includes a preamble and header transmitted at a first power level and at least one special data symbol and a payload transmitted at a second power level that is less than the first power level. The special data symbol resides between the preamble or header and the payload and is usable by the second PLC device for processing of the payload.

Abstract: Aspects of a method and system for efficient full resolution correlation may include correlating a first signal with a second signal at a rate corresponding to a first discrete signal, wherein each sample of the first signal may be generated by summing a plurality of consecutive samples from the first discrete signal, and the second signal may be generated by summing the plurality of consecutive samples from a second discrete signal. The correlating may be performed by a matched filter and/or a correlator. The first signal comprising N samples may be generated by summing L consecutive samples for each of the N samples from the first discrete signal comprising N*L samples. The second signal comprising N samples may be generated by summing L consecutive samples for each of the N samples from the second discrete signal comprising N*L samples.