Abstract: Methods and systems for a voltage-controlled oscillator (VCO) with a leaky wave antenna are disclosed and may include transmitting wireless signals via one or more leaky wave antennas in one or more tank circuits coupled to one or more VCOs. The VCOs may be two-point modulated. Two modulating signals may be communicated to the one or more VCOs via varactors coupled to tank circuits on the one or more VCOs. The varactors may include CMOS transistors with source and drain terminals shorted together. The one or more leaky wave antennas may be integrated on the chip, on a package to which the chip is affixed, or on a printed circuit board to which the chip is affixed. The VCOs may be integrated in a phase-locked loop and an output of the one or more VCOs in the phase-locked loop may be fed back via a multi-modulus detector.

Abstract: A disclosed method comprises calibrating adaptive offset values in an open-circuit voltage lookup table, a temperature lookup table, and an age lookup table, and then determining a present charge of the battery utilizing an open-circuit voltage of the battery and a temperature of the battery, determining a low-voltage-alarm charge of the battery utilizing a discharge current of the battery and an age of the battery, and utilizing the present charge and the low-voltage-alarm charge to estimate the run time of the battery. Utilizing the open-circuit voltage, temperature, and age comprises looking up a present battery capacity, temperature coefficient, and ageing coefficient in lookup tables, and adjusting the present battery capacity, temperature coefficient, and ageing coefficient by the respective offset values adaptive to the battery.

Abstract: A communication technique facilitates transmission of low rate traffic over communication nodes. The nodes may be, for example, MoCA nodes. The communication happens while keeping the nodes in ultra low power mode. Accordingly, the technique increases the communication capabilities and coverage of networked nodes without impacting the overall power consumption budget. In one implementation, the technique includes encapsulating a datagram into a datagram information element, appending the datagram information element to a discovery request message, and sending the discovery request message to a network controller. The network controller extracts the datagram information element and forwards it (e.g., by broadcasting) to ultra low powered nodes, for example in an admission control frame.

Abstract: A method for accurately estimating a run time of a battery utilized by an electronic device. The method comprises determining a starting battery capacity utilizing an open-circuit voltage of the battery, determining a battery capacity decline rate utilizing a load-condition voltage of the battery, and determining a low-voltage-alarm battery capacity during an active operation of the electronic device. The method further comprises utilizing the starting battery capacity, the battery capacity decline rate, and the low-voltage-alarm battery capacity to estimate the run time of the battery which may be determined by dividing the difference of the starting battery capacity and the low-voltage-alarm battery capacity by the battery capacity decline rate. One embodiment utilizes an open-circuit voltage lookup table, a load-condition voltage lookup table, and a low-voltage-alarm lookup table that are configured for use with a certain type of battery.

Abstract: Embodiments of power sourcing equipment (PSE) utilizing AC disconnect are provided herein. In one embodiment, a PSE is provided that includes a DC supply configured to provide a DC voltage over a data communications medium, a controller configured to provide an AC disconnect signal over the data communications medium, and a parallel inductor-capacitor (LC) circuit coupled between the DC supply and the data communications medium. The parallel LC circuit is configured to isolate the DC supply from the AC disconnect signal. In another embodiment, a PSE is provided that includes a DC supply configured to provide a DC voltage at an output, an inductor coupled between the output of the DC supply and a data communications medium, and a capacitor coupled between the data communications medium and ground. The inductor and capacitor form a series LC circuit configured to generate an AC disconnect signal.

Abstract: It may be determined via monitoring whether a first link partner and/or a second link partner coupled via an Ethernet link has trained or refreshed circuitry and/or has updated at least one parameter. Based on the determination, a corresponding link partner may be trained, refreshed and/or updated. One or more of an echo canceller, a far-end crosstalk canceller and a near-end crosstalk canceller for one or more channels may be configured based on the training, refreshing and/or updating. One or more channels may be silent and/or one or more may be active. Link partners may communicate via one or more of in-band signaling, out-of-band signaling to determine which link partner may monitor and/or which may control or initiate operation. The controlling link partner may be assigned a master mode of operation. Training, refreshing and/or updating for the monitoring link partner may be based on a timer.

Abstract: According to an exemplary embodiment, a memory array arrangement includes a plurality of word lines, where at least two of the plurality of word lines are concurrently active word lines. Each of the plurality of word lines drive at least one group of columns. The memory array arrangement also includes a multiplexer for coupling one memory cell in a selected group of columns to at least one of the plurality of sense amps, thereby achieving a reduced sense amp-to-column ratio. The memory array arrangement further includes a plurality of I/O buffers each corresponding to the at least one of the plurality of sense amps. The memory array arrangement thereby results in the plurality of word lines having reduced resistive and capacitive loading.

Abstract: A video and graphics system on an integrated circuit chip includes an integrated system bridge controller to interface a CPU with devices internal to the system as well as external peripheral devices. The system bridge controller is capable of performing format conversion between big-endian data and little-endian data. The system bridge controller includes a PCI bridge to interface with PCI devices, an I/O bus bridge to interface with I/O devices such as RAM, ROM, flash memory and 68000-compatible peripheral devices, and a CPU interface block to interface the CPU to video processing devices on the integrated circuit chip such as an MPEG video decoder.

Abstract: Aspects of a method and system for generating quadrature signals utilizing an on-chip transformer are provided. In this regard, a pair of phase-quadrature signals may be generated from a single-phase signal via a transformer, one or more variable capacitors, and one or more variable resistors integrated on-chip. The transformer may comprise a plurality of loops fabricated in a plurality of metal layers in the chip. Each of the one or more variable capacitors may comprise a configurable capacitor bank and each of the one or more variable resistors may comprise a configurable resistor bank. The one or more capacitor banks may be programmatically configured on-chip, based on a frequency of the single-phase signal. The one or more resistor banks may be programmatically configured on-chip, based on a frequency of said single-phase signal.

Abstract: A system and method for energy savings on a PHY/MAC interface for energy efficient Ethernet. Power savings for a PHY due to low-link utilization can also be realized in the higher layer elements that interface with the PHY. In one embodiment, subrating is implemented on a MAC/PHY interface to match a subrating of the PHY with a remote link partner. This subrating is less than the full capacity rate and can be zero.

Abstract: Methods and systems for filters embedded in an integrated circuit package are disclosed and may include controlling filtering of signals within an integrated circuit via one or more filter components embedded within a multi-layer package bonded to the integrated circuit. The one or more filter components may be electrically coupled to one or more switchable capacitors within the integrated circuit. The filter components may include transmission line devices, microstrip filters, transformers, surface mount devices, inductors, and/or coplanar waveguide filters. The filter components may be fabricated utilizing metal conductive layers and/or ferromagnetic layers deposited on and/or embedded within the multi-layer package. The integrated circuit may be electrically coupled to the multi-layer package utilizing a flip-chip bonding technique.

Abstract: Signal synchronizers synchronize input signals with a clock signal. The input of each synchronizer is connected to a first input and the output of each synchronizer is connected to a second input of a respective first gate arrangement. The first gate arrangements provide an output signal only if there is an input signal on the first input and none on the second input or vice versa. The outputs of each of the first gate arrangements is connected to respective inputs of a second gate arrangement, which provides an output signal if there is a signal on any of its inputs. The output of the second gate arrangement is connected to a third gate arrangement which operates such that the clock signal to the synchronizers is only enabled when there is a change to the state of a signal received at the input of at least one of the synchronizers.

Abstract: Embodiments provide a method and apparatus for performing time division duplex communication, such as may be performed over a wireless communications network. In the embodiments a first circuit pathway is used to transmit a first radio frequency signal in a transmission mode and a second circuit pathway is used to receive a second radio frequency signal in a reception mode. In the reception mode, the first radio frequency signal is switched to an alternate circuit pathway. This may be performed by a radio frequency integrated circuit or by other control circuitry. Switching to an alternate circuit pathway reduces leakage of the first radio frequency signal into the second radio frequency signal.

Abstract: One embodiment provides a system for calculating a checksum for a packet. During operation, the system receives a packet, pads the received packet with a number of bits having predetermined values, and calculates an initial checksum value for the padded packet. Subsequently, the system calculates a final checksum for the original packet by reversing the initial checksum value using the padded bits with predetermined values.

Abstract: Methods and systems for a configurable finite impulse response (FIR) filter using a transmission line as a delay line are disclosed and may include selectively coupling one or more taps of a multi-tap transmission line to configure delays for one or more finite impulse response (FIR) filters to enable transmission and/or reception of signals. The delays may be configured based on a location of the one or more selectively coupled taps on the multi-tap transmission line. The FIR filters, which may include one or more stages, may be impedance matched to the selectively coupled taps. The multi-tap transmission line may be integrated on the chip, or a package to which the chip is coupled. The multi-tap transmission line may include a microstrip structure or a coplanar waveguide structure, and may include ferromagnetic material. The distortion of signals in the chip may be compensated utilizing the FIR filters.

Abstract: A universal authentication token is configured to securely acquire security credentials from other authentication tokens and/or devices. In this manner, a single universal authentication token can store the authentication credentials required to access a variety of resources, services and applications for a user. The universal authentication token includes a user interface, memory for storing a plurality of authentication records for a user, and a secure processor. The secure processor provides the required cryptographic operations to encrypt, decrypt, and/or authenticate data that is sent or received by universal token. For example, secure processor may be used to generate authentication data from seed information stored in memory.

Abstract: An energy efficient sleep signature in power over Ethernet. In one embodiment, a signature of a powered device is first detected. It is then determined whether the detected signature is indicative of an unknown powered device. In one example, a detected signature of an approximately 25 k? impedance is indicative of an unknown powered device. Where the detected signature is indicative of an unknown powered device a normal PoE startup powering process can be used that includes a conventional detection, classification and powering process. Where the detected signature is indicative of a powered device that was previously known to the PSE, then powering of the PD can proceed with a fast-restart powering method that retains previous powering parameters.

Abstract: A multi-ported memory that supports multiple read and write accesses is described. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for read operation(s) and write operation(s) to be received during the same clock cycle. In the event that an incoming write operation is blocked by read operation(s), data for that write operation may be stored in one of a plurality of cache banks included in the multi-port memory. The cache banks are accessible to both write and read operations. In the event than the write operation is not blocked by read operation(s), a determination is made as to whether data for that incoming write operation is stored in the memory bank targeted by that incoming write operation or in one of the cache banks.

Abstract: A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.

Abstract: A computing system includes a first central processing unit (CPU) and a second CPU coupled with the first CPU and with a host processor. In response to a request by the host processor to boot the second CPU, the first CPU is configured to execute secure booting of the second CPU by decrypting encrypted code to generate decrypted code executable by the second CPU but that is inaccessible by the host processor.