Abstract: A method and system is provided for sharing of bandwidth on intermediate frequency cabling connections between indoor and outdoor units of a MIMO microwave communications system. Phase locked loop design assists in creating synchronization signals to be transmitted over the cable connecting the indoor units and outdoor units.

Abstract: An antenna array structure includes a plurality of antennas, wherein a first antenna has a first geometric shape, provides a first radiation pattern, and has a first frequency bandwidth. A second antenna has a second geometric shape to provide a second radiation pattern and has a second frequency bandwidth. The first and second frequency bandwidths at least partially overlap to include channels of interest. An antenna processing circuit sends one or more transmit signals to one or more of the antennas for transmission via one or more of the channels of interest and receives one or more receive signals from the one or more of the antennas or from another one or more of the antennas via the one or more of the channels of interest or from another one or more of the channels of interest.

Abstract: Systems and methods are presented for reducing the impact of high load and aging on processor cores in a processor. A Power Management Unit (PMU) can monitor aging, temperature, and increased load on the processor cores. The PMU instructs the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.

Abstract: Short training field (STF) for use within single user, multiple user, multiple access, and/or MIMO wireless communications. An STF design as is made such that the power associated with the tone indices at the edges of the STF design is relatively less than the power associated with the tone indices more centrally located within the STF design. Also, when multiple respective operational modes are supported (e.g., 1 MHz and 2 MHz), the respective STF designs corresponding to those respective operational modes have a great deal of similarity. For example, the respective STF designs for different respective operational modes may have certain common STF tone indices among those respective STF designs.

Abstract: Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

Abstract: A communication device's processor generates an OFDMA packet that includes different information for different recipient devices. The processor transmits, via a communication interface, different portions of the OFDMA packet via different channels. Initially, the processor transmits a first at least one field of the OFDMA packet intended for a first recipient device via the first channel. Then, the processor transmits a second at least one field of the OFDMA packet intended for the first recipient device via the first channel while simultaneously transmitting at least one other field of the OFDMA packet intended for a second recipient device via a second channel. This staggered transmission of different portions of the OFDMA packet via different channels allows a recipient device to classify different portions of the OFDMA packet and to determine which portions are intended for that recipient device.

Abstract: One or more processors and/or one or more circuits may be operable to configure one or more virtual machines and a hypervisor for controlling the one or more virtual machines. The virtual machines and the hypervisor may be distributed across a plurality of network devices. A sub-hypervisor may be configured within each of the virtual machines utilizing the hypervisor. Load information of the network devices may be communicated to the hypervisor utilizing the sub-hypervisors. The virtual machines may include threads, may be load balanced utilizing the hypervisor, dynamically configured utilizing the hypervisor based on changes in the network devices, and scaled by the distribution of the virtual machines across the network devices. Information from the processing of data may be received in the virtual machines. The network devices may include a plurality of: servers, switches, routers, racks, blades, mainframes, personal data assistants, smart phones, desktop computers, and/or laptop devices.

Abstract: Embodiments provide solutions to reduce power utilization (either at individual cable modems or in the overall network) in future cable modem networks. Particularly, embodiments seek to reduce power utilization at individual cable modems and in the overall network, by allocating upstream frequency bands and/or transmission modulation schemes among cable modems while accounting for cable loss experienced by individual upstream cable modem transmissions. According to embodiments, frequency spectrum and modulation scheme allocation techniques are provided to optimize power utilization and enable lower upstream transmission power by cable modems while maintaining similar signal strength of received signals or lower signal strength with reduced SNR requirements using lower capacity modulation at the headend.

Abstract: A system and method for efficient buffer management for banked shared memory designs are provided. In one embodiment, a controller within the switch is configured to manage the buffering of the shared memory banks by allocating full address sets to write sources. Each full address set that is allocated to a write source includes a number of memory addresses, wherein each memory address is associated with a different shared memory bank. A size of the full address set can be based on a determined number of buffer access contenders.

Abstract: Apparatus, methods, computer software and computer program products are provided for tuning a user equipment antenna to simultaneously operate at more than one resonant frequency by combining a first electrical load and a first frequency selective component to tune the antenna to a first resonant frequency with respect to signals in a first frequency range, and combining a second electrical load and a second frequency selective component to tune the antenna to a second resonant frequency with respect to signals in a second frequency range. The first electrical load, the second electrical load, the first frequency selective component and the second frequency selective component act to tune the antenna to operate simultaneously at the first resonant frequency and the second resonant frequency.

Abstract: A request for a unit of video information is received from a remote video receiver. An initial transmission rate for the unit of video information is determined based at least in part on a decoder model and a typical steady-state transmission rate for the unit of video information. The initial transmission rate is faster than the typical steady-state transmission rate. For a first time period after receiving the request, a first portion of the unit of video information is transmitted to the remote video receiver at the initial transmission rate. The first time period, the initial transmission rate, or both are determined so as not to overflow an input buffer that is based at least in part on the decoder model. For a second time period after the first time period, a second portion of the unit of video information is transmitted to the remote video receiver at the typical steady-state transmission rate.

Abstract: A system and method to provide a protection ring in an Audio Visual Bridging (AVB) network is provided. The method includes the steps of monitoring a first status of links coupled to a plurality of devices in a ring network, receiving a second status of links of other devices in the ring network, and signaling devices in the ring network to generate a logical loop-free topology based upon a stored static physical configuration, the first status of the links and the second status of links of other network devices in the ring network. The method also includes the step of determining an allocation of flows to links based on stored flow characteristics. Determining an allocation of flows to links includes programming a transmit scheduler to provide a first percentage of bandwidth for Audio Video Bridging (AVB) flows while reserving a second percentage of bandwidth for non-AVB flows.

Abstract: A wireless power system can include wireless power receive circuitry for generating power from a wireless signal, and a wireless power transceiver for communicating with a wireless power transmission unit. The wireless power system can transition from an idle state to different power management states depending on whether or not communication has been established with the wireless power transmission unit. Different modules can be activated, different supply voltages, and different clock signal rates can be used in different power management states.

Abstract: A secure integrated circuit (IC) to provide access to an electronic storage, the secure IC including a memory and a processor. The processor may generate a first key and a second key, and enable storing the first key in the memory and storing the second key in a device memory of a device. The processor may then receive the second key from the device when the device wants to access the electronic storage, and grant the device access to the electronic storage by using the first key and the second key received from the device.

Abstract: A voltage controlled oscillator (VCO) with low phase noise and a sharp output spectrum is desirable. The present disclosure provides embodiments of LC tank VCOs that generate output signals with less phase noise compared with conventional LC tank VCOs, while at the same time limiting additional cost, size, and/or power. The embodiments of the present disclosure can be used, for example, in wired or wireless communication systems that require low-phase noise oscillator signals for performing up-conversion and/or down-conversion.

Abstract: A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, a device encodes information using a low density parity check (LDPC) code to generate an LDPC coded signal and transmits the LDPC coded signal to another communication device. in other examples, a device receives an LDPC coded signal from another communication device and decodes the LDPC coded signal using an LDPC matrix. The LDPC matrix includes a left hand side matrix and a right hand side matrix (e.g., having CSI (Cyclic Shifted Identity) sub-matrices on a main diagonal and another diagonal adjacently located to the main diagonal).

Abstract: A near field communications (NFC) device is disclosed that intelligently routes NFC data from a NFC device between multiple user interfaces based upon a power level of its internal batteries. The communications device utilizes a communications device user interface to send and/or receive the NFC data from the NFC device when its internal batteries are sufficient to operate the communications device user interface. The communications device begins to route some of this NFC data from being sent and/or received by the communications device user interface to a NFC user interface as its internal batteries deplete. Eventually, all of the NFC data will be sent to and/or received by the NFC user interface as the internal batteries of the communications device become so depleted that they are unable to reliably operate the communications device user interface.

Abstract: Protocol adaptation layer for wireless communications. Communication devices that include one or more radio modules operable in accordance with multiple communication protocols establish communications using one communication protocol and then switch to another communication protocol. This switching to another communication protocol may be performed based on a variety of factors including effectuating communications of higher throughput, supporting uni-directional communications vs. bi-directional communications, or any other desired factor. In some embodiments, various communication devices include two radio modules that are each implemented to operate in accordance with one particular communication protocol. Alternatively, a multi-protocol capable radio module may support and operate in accordance with more than one communication protocol. Examples of possible communication protocols include those compliant with Bluetooth, IEEE 802.11, and/or 802.15.3c.

Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract: A frequency synthesizer includes circuitry configured to generate two or more feedback clocks based on the oscillation signals output from a voltage-controlled oscillator. The circuitry also modulates the feedback clocks based on fractional offsets from a reference clock frequency for input into two or more phase and frequency detectors. Multiple charge pump circuits receive inputs from these phase and frequency detectors. The current from these charge pumps is summed and input to a low pass filter. The output of the filter represents an average of the time difference between the reference clock and the multiple feedback clocks.