Abstract: Adaptive multi-standard video coder supporting adaptive standard selection and mid-stream switch-over. Automatic or semi-automatic selection and reselection between various respective communication protocols or standards (e.g., or profiles of such protocols or standards, subsets of such protocols or standards, etc.) may be made based on any of a number of local and/or remote considerations. For example, characteristics associated with one or more other devices, communication links, communication networks, etc. within a communication system may direct the automatic or semiautomatic selection and reselection between such communication protocols or standards (e.g., or profiles thereof, or subsets thereof, etc.). Also, characteristics associated with local operating conditions (e.g., available processing resources, available memory, etc.) this may be used in accordance with making such selection and reselection.

Abstract: Devices and a system for synchronizing time between a centralized controller device and at least one subscriber device on a fiber access network. The control layer of a network device is expanded, and additional messaging control is added via the transmission of data frames. The expansion prevents reliance on a physical layer signal. The time synchronization also allows a time stamp to be incorporated into a message. Thus, bandwidth is not wasted by simply transmitting a time stamp by itself. In an embodiment, the centralized controller device measures the time difference between the time at which a particular ranging request is transmitted and the time at which the particular ranging request is received. The time difference represents the time adjustment value for the particular subscriber device and allows the device to synchronize its time with that of the centralized controller device.

Abstract: An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: A system for processing signals is disclosed and may include a single chip having an integrated Bluetooth radio and an integrated FM radio. The single chip may include at least one processor that enables selecting from a range of FM channels, a particular frequency for one of the FM channels based on an intermediate frequency (IF). The particular frequency may be selected so that it is an integer multiple of a channel spacing between neighboring allocated FM channels within the range of FM channels, and may be offset by at most one-half the channel spacing. The at least one processor may enable determining a frequency error of the selected particular frequency for the one of the FM channels. The at least one processor may also enable determining, whether the particular frequency includes an on-frequency channel based on the determined frequency error.

Abstract: A radio receiver is described that processes multiple wireless standards using a single antenna according to embodiments of the invention. The radio receiver includes a single antenna, and a low noise amplifier that is connected to the antenna, without an intervening power divider or power splitter. The output of the low noise amplifier feeds multiple wireless receivers in a parallel arrangement that are operating according to different communications standards, including for example a Bluetooth and a WLAN 802.11. Additional wireless standards and their corresponding receivers could be added as well. The input impedance of the low noise amplifier defines the impedance seen by the antenna, regardless of which operational standard is actually in use. Each signal path includes an additional low noise amplifier having a gain that can be customized for the particular signal path and receiver in use, and which also improves the reverse isolation between signal paths.

Abstract: A method and system for a double search algorithm of user group selection for multiuser MIMO downlink transmission are provided. The use of optimal brute-force user group selection may require high computational expense. A first search operation may be based on a first user having a channel gain greater than that of other users, while a second search operation may be based on a second user having a channel gain greater than that of the remaining users. A maximized system capacity may be determined based on the maximized system capacities determined in the first and second search loop. A receiver pair associated with the maximized system capacity may be selected as the user group. The double search algorithm may reduce the computational complexity while achieving performances that may exceed the TDMA scheme and be similar to that of systems with ideal CSI at the transmitter.

Abstract: An integrated circuit includes a first integrated circuit die having a first circuit and a first intra-chip interface and a second integrated circuit die having a second circuit and a second intra-chip interface and a remote interface, wherein the first intra-chip interface and the second intra-chip interface electro-magnetically communicate first signals between the first circuit and the second circuit, and wherein the remote interface is coupled to engage in electromagnetic communications with a remote device. In an embodiment of the present invention, a shielding element shields the electromagnetic communications with the remote device from the electromagnetic communication of the first signals. In other embodiments, antenna beam patterns or differing polarizations are used to isolate the electromagnetic communications with the remote device from the electromagnetic communication of the first signals.

Abstract: A beamforming radio frequency (RF) circuit includes a plurality of antennas, a plurality of amplifiers and an adjust module. The plurality of antennas is operably coupled to interrelate a plurality of beamformed signal components with a beamformed signal. The plurality of amplifiers is operably coupled to interrelate the plurality of beamformed signal components with a plurality of adjusted signal components. The adjust module is operably coupled to interrelate coordinates of a signal with the plurality of adjusted signal components.

Abstract: A multicast call processing unit receives a request from a requester, determines if the request is associated with a multicast function, identifies a plurality of destinations defined by the multicast function and establishes communication link between the requester and the plurality of destinations. In one embodiment, the call processing unit authenticates the plurality of destinations before establishing a communication link between them and the requester. If the request from the requester is not associated with the multicast function, then the call processing unit establishes a communication link between the requester and a single destination. In another embodiment, a supervisor manages the plurality of destinations.

Abstract: A transceiver includes an RF receiver section having a plurality of RF receiver stages configured in parallel, and a configurable RF transmitter section. The plurality of RF receiver stages are selectively enabled in response to a control signal. The configurable RF transmitter section is configured to operate in one of: a mixed signal mode of operation and a phase modulation mode of operation, in response to the control signal.

Abstract: Presented herein are system(s) and apparatus for a memory access unit for accessing data for a module. The memory access unit comprises an output port for providing access requests for lists of addresses in a memory over a link to a memory controller.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.

Abstract: According to one embodiment, an input control unit to provide isolation and electrostatic discharge (ESD) protection for a circuit in an RF transceiver comprises a switching device coupled between an input of the circuit and ground. The switching device is configured to provide ESD protection while the circuit is activated. The switching device is further configured to ground the input while the circuit is non-activated, thereby concurrently isolating the input and providing ESD protection. A method for providing isolation and ESD protection for a circuit in an RF transceiver comprises activating the circuit, providing ESD protection while the circuit is activated, deactivating the circuit, and coupling an input of the circuit to ground, thereby concurrently isolating the input and providing ESD protection while the circuit is non-activated. The method and switching device can be used to provide isolation and ESD protection to receive bands in the RF transceiver.

Abstract: The present invention provides a method and apparatus for initiating a multiple input multiple output (MIMO) communication. The method and apparatus includes processing that begins by transmitting a frame formatted in accordance with a default MIMO active transmitter-receiver antenna configuration to a target receiver. The processing continues by receiving at least one response frame from the target receiver. The processing continues by determining a number of receiver antennas of the target receiver from the at least one response frame.

Abstract: A transmitting system includes a clock system and a data system. The clock system is configured to receive a clock having a first value and produce a control signal having a second, different value and an output clock having the first value. The data system is configured to receive data and the control signal and to align the data with the output clock, based on the control signal, to produce output data. The clock system includes a driver configured to produce the output clock, a divider configured to divide the received clock, and a phase interpolator configured to rotate the divided clock to produce the control signal. Also, the data is parallel data, and the data system includes a multiplexer configured to receive the parallel data and to use the control signal to serialize the parallel data as the aligned data and a driver configured to produce the output data.

Abstract: Improved master latch for high-speed slicer providing enhanced input signal sensitivity. A pre-charging circuit injects charge into the sources of the differential pair of a latch that samples the input signal during odd clock cycles. This reduces the gate-to-source voltage of the sampling pair, making them less sensitive to data bits latched by a second parallel master latch in odd clock cycles. The injected charge dissipates before the sampling pair is needed to fully sample the input signal in even clock cycles. The pre-charging circuit includes a current mirror, a current source and a transistor that couples the current source to the current mirror during odd clock cycles. A shunt peaked amplifier with excess peaking boosts the high-frequency content of a differential input signal relative to its low-frequency content. Capacitors cross-couple the gates and drains of the differential sampling pair.

Abstract: An output stage comprising a current mode line driver, a voltage mode line driver, and a center-tapped transformer for coupling data provided by the line drivers to a transmission line is provided herein. The output stage is configured to operate in a backwards compatible Ethernet communication device. For example, the Ethernet communication device is configured to support 10G Ethernet and legacy Ethernet modes of 10BASE-T, 100BASE-T, and 1000BASE-T. The current mode line driver can be utilized while operating in the 10G Ethernet mode to provide high linearity. The voltage mode line driver can be utilized while operating in legacy mode to conserve power. In order to accommodate the use of two different line drivers, a switch and/or a voltage regulator is used to couple/decouple a dc voltage to a center-tap of the transformer based on which of the two different line drivers is currently active.

Abstract: A method, system and computer program product in a downstream line card of a Cable Modem Termination System (CMTS) for managing downstream traffic for channels and bonded channel groups is provided herein. The method comprises the step of receiving packets for transmission to cable modems and classifying each packet to a flow based on class of service associated with the packet. The method further includes the step of storing the packets in flow queues based, wherein a flow queue is selected based on a flow a packet is associated with and wherein each flow corresponds to a single flow queue.

Abstract: A method for establishing a virtual channel between network devices is disclosed. In the case of a local network device establishing a virtual channel with a remote network device, a virtual channel request message is sent from the local network device to the remote network device. A virtual channel acknowledgement message and a remote capability list are received and a virtual channel resume message and a local capability list are sent. The virtual channel is then enabled. In the case of a remote network device establishing a virtual channel with a local network device, a virtual channel request message is received from a local network device by a remote network device. A virtual channel acknowledgement message and a remote capability list are sent and a virtual channel resume message and a local capability list are received. The virtual channel is then enabled.