Abstract: Explicit feedback format within single user, multiple user, multiple access, and/or MIMO wireless communications. A beamformer provides a first communication to a beamformee, and based thereon, the beamformee may ascertain certain characteristics associated with the type and format of feedback to be provided to the beamformee via a second communication from the beamformee to the beamformer. For example, the first communication may include indication of a current operational mode, such as whether it is in accordance with single-user multiple input multiple output (SU-MIMO) or multi-user multiple-input-multiple-output (MU-MIMO). Also, the first communication may indicate a requested steering matrix's rank to be employed in accordance with subsequent beamforming by the beamformer. Also, additional information such as that pertaining to per-tone SNR values for each respective space-time stream, per-tone or per-sub-band eigen-values, the particular channel width being employed (e.g., 20, 40, 80, or 160 MHz), etc.

Abstract: A device includes a first integrated circuit, a second integrated circuit and an RF bus controller. Each of the first and second ICs includes a radio frequency (RF) bus transceiver. The RF bus controller is coupled to control intra-device RF communications between the RF bus transceivers of the first and second ICs.

Abstract: A transmitter capable of operating according to a first standard that does not interfere with a nearby frequency generator operating according to a second standard. The transmitter comprises an oscillator, a frequency divider, a mixer, and a filter. The oscillator is configured to output a first frequency that is outside of a frequency harmonic of the frequency generator. The frequency divider is coupled to the oscillator and divides the first frequency by a selective divide ratio to produce a second frequency. The mixer is configured to receive the first and second frequencies, which combines them to produce a mixed frequency. The filter is then used to filters the mixed frequency to obtain the higher portion of the mixed frequency. The divide ratio of the frequency divider is selected base on the desired output frequency of the transmitter such that a 2.4 GHz or 5 GHz ISM band frequency is achieved.

Abstract: A dual band antenna includes a far field antenna structure for facilitating the communication of first data with a remote device via far field signaling in a millimeter wave band. A near field antenna structure facilitates the communication of second data with a remote device via near field signaling in a near field band. The far field antenna structure and the near field antenna structure share at least one common antenna element.

Abstract: An RF integrated circuit (IC) includes a first IC port for coupling a first transmit signal in a first frequency band to at least one external device and a second IC port for coupling a second transmit signal in a second frequency band to the at least one external device. A transmitter module responds to outbound data to generate the first transmit signal in a first mode of operation and to generate the second transmit signal in a second mode of operation, wherein the transmitter module generates the first transmit signal and the second transmit signal in a selected one of a plurality of wireless telephony formats based on a control signal, and wherein the plurality of wireless telephony formats includes a UMTS format and at least one non-UMTS format.

Abstract: An apparatus, a method, and a system are provided to calibrate an offset in an amplifier. The apparatus can include an amplifier, a voltage control unit, a comparator, and a processing unit. The amplifier can have four terminals: a positive differential input (VIN+), a negative differential input (VIN?), a positive differential output (VOUT+), and a negative differential output (VOUT?). The voltage control unit can be configured to adjust a first voltage on VOUT+ and a second voltage on VOUT?. The comparator can be configured to compare the first voltage on VOUT+ to the second voltage on VOUT? when VIN+ and VIN? are coupled to a common voltage. Further, the processing unit can be configured to provide a control signal to the voltage control unit based on the comparison of the first and second voltages on VOUT+ and VOUT?, respectively.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: In RF transceivers, a method and system for using phase shift key (PSK) sync word for fine tuning frequency adjustment are provided. One aspect of the invention provides for adjusting a local oscillator frequency in a radio frequency (RF) receiver when a residual DC offset remains after a coarse frequency offset adjustment if performed. The fine adjustment may be necessary because of the synchronization required with a PSK-based modulated portion of a Bluetooth packet. A residual phase shift detected in a sync sequence portion of the Bluetooth packet may be utilized to determine a residual or fine frequency adjustment. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.

Abstract: Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic channel. A receiver may then receive the laser signal from the fiber optic channel and convert it into an electrical signal. Multi-carrier modulation may be applied to existing fiber channels, which may be of lower quality. Existing fiber channels may have characteristics which prevent or restrict the transmission of data using intensity modulation at certain frequencies. An adaptive multi-carrier modulation transmitter may characterize an existing fiber optic channel and ascertain the overall characteristics of the channel. The transmitter and receiver can then be configured to use various bandwidths and various modulations in order to match the transfer characteristic of the fiber channel.

Abstract: An RF transmitter includes a Cartesian to polar conversion section, a PLL, a DAC module, a mixing module, and a PA module. The Cartesian to polar conversion section converts a Cartesian based symbol stream into a polar based symbol stream. The PLL generates an oscillation when the RF transmitter is in a Cartesian mode or a phase modulated oscillation based on phase modulation information of the polar based symbol stream when the RF transmitter is in a polar mode. The mixing module mixes an analog Cartesian based signal with a local oscillation to produce a Cartesian based up converted signal when the RF transmitter is in the Cartesian mode and mixes an analog amplitude signal with a phase modulated local oscillation to produce a polar based up converted signal when the RF transmitter is in the polar mode.

Abstract: In wireless communications such as in the Bluetooth communication system, an execution unit sequentially receives software instructions for execution. Prior to completing each instruction, the execution unit issues an interrupt indicating the upcoming completion of the instruction execution and awaits receipt of the next instruction. A Link Manager issues limited instructions, and a Link Controller includes a hardware execution unit for executing the limited instructions. A processing unit in the Link Manager performs remaining functions under control of a software program.

Abstract: A networking method, microchip, and device are described in which a first security engine may be associated with a chaining port and configured to perform an inner processing for an inner layer of encryption for a frame of data, while a second security engine may be associated with an external port and configured to perform an outer processing for an outer layer of encryption for the frame of data. Control logic may be configured to instruct the first security engine to execute both a transmit operation and a receive operation of the frame of data in association with the inner processing.

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract: Systems and methods for securing a credential generated by or stored in an authentication token during an attempt to access a service, application, or resource are provided. A secure processor receives a credential from an authentication token and securely stores the credential. The secure processor then verifies the identity of the individual attempting to use the authentication token and cryptographically verifies the identity of the server being accessed. The credential is only released for transmission to the server if both the identity of the individual and the identity of the server are successfully verified. Alternatively, a secure connection is established between the secure processor and the server being accessed and a secure connection is established between the secure processor and a computing device. The establishment of the secure connections verifies the identity of the server. After the secure connections are established, the identity of the user is verified.

Abstract: An electronic communication network supports delivery of video program Internet protocol packets and includes a source device, a first recipient device, and a second recipient device. The source device transmits both first and second video program Internet protocol packets. The first recipient device is assigned as positive acknowledgment leader by the source device and the second recipient device that is assigned as negative acknowledgement leader by the source device. The first recipient device is operable to transmit to the source device a positive acknowledgment of receipt of the first video program Internet protocol packet. The second recipient device is operable to transmit to the source device a negative acknowledgment of non-receipt upon not receiving the first video program Internet protocol packet.

Abstract: A method and apparatus for buffering an encoded signal having a plurality of codewords for a turbo decoder is provided. The method comprises de-interleaving each sub-block of the codeword received at the turbo-decoder; and storing LLRs of the de-interleaved codeword LLRs into an input buffer. Thereafter, each of punctured locations, if any, in the de-interleaved codeword is indicated to a read logic for enabling the latter to fill in each of those locations with a pre-determined LLR value as and when a read request corresponding to one of those locations arrives. This method obviates the need for storing the pre-determined LLRs at the punctured locations into the input buffer and thereby cuts down the input latency of turbo decoder significantly for higher code rates.

Abstract: A method and system to transfer a data stream from a data source to a data sink are described herein. The system comprises a trigger core, a plurality of dedicated buffers and a plurality of dedicated buses coupled to the plurality of buffers, trigger core, the data source and the data sink. In response to receiving a request for a data transfer from a data source to a data sink, the trigger core assigns a first buffer and a first bus to the data source for writing data, locks the first buffer and first bus, releases the first buffer and the first bus upon indication from the data source of completion of data transfer to the first buffer, assigns the first buffer and first bus to the data sink for reading data and assigns a second buffer and second bus to the data source for writing data thereby pipelining the data transfer from the data source to the data sink.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: An integrated circuit package including a first metal layer coupled to a bonding pad, a first redistribution layer coupled to the bonding pad, and a RDL to Metal (RTM) via coupled to a first surface of the metal layer and further coupled to a first surface of the first RDL is described. The IC package may further include additional metal layers and redistribution layers.

Abstract: Certain aspects of a multi-channel signal synchronizer may comprise receiving a plurality of clock signals from a plurality of clock signal sources, wherein a portion of the received plurality of clock signals may be out of synchronization with a remaining portion of the received plurality of clock signals. A plurality of data signals may be received from a plurality of data signal sources, wherein a portion of the received plurality of data signals may be out of synchronization with a remaining portion of the received plurality of data signals. The received portion of plurality of clock signals and data signals may be synchronized to the received remaining portion of plurality of clock signals and data signals utilizing bit alignment and sample alignment. A plurality of synchronized output signals may be generated based on the synchronized received plurality of clock signals and synchronized received plurality of data signals.