Abstract: A communication system is described in which a receiver allocated to a sector of a communication network receives signals via all antennas of the network regardless of the sector allocation of the antenna. The system includes multiple antennas configured to form numerous antenna sets. Each antenna set is allocated to one of a number of sectors of a communication network. The system includes numerous modems or receivers, and each modem is coupled to an antenna set of a sector. The system includes a memory device coupled to the modems. The memory device includes signal processing information shared among the modems of the system. The signal processing information allows each modem to receive communications from subscriber stations in any sector via any of the system receive antennas.

Abstract: Aspects of a method and system for frequency-shift based chip-to-chip communications may include receiving and/or generating modulation control information and demodulation control information within a chip comprising one or more receivers and one or more transmitters. One or more modulation frequencies may be adjusted and utilized to generate transmit signals by the one or more transmitters based on the received modulation control information, wherein the one or more modulation frequencies may be distinct. One or more demodulation frequencies may be adjusted and utilized to generate intermediate frequency signals by the one or more receivers based on the received demodulation control information wherein the one or more demodulation frequencies may be distinct. The modulation control information and the demodulation control information may be received via a communication device comprising said chip.

Abstract: The present invention relates to a mobile set integrating a memory efficient data storage system for the real time recording of voice conversations, data transmission and the like. The data recorder has the capacity to selectively choose the most relevant time frames of a conversation for recording, while discarding time frames that only occupy additional space in memory without holding any conversational data. The invention executes a series of logic steps on each signal including a voice activity detector step, frame comparison step, and sequential recording step. A mobile set having a modified architecture for performing the methods of the present invention is also disclosed.

Abstract: A handheld computing device includes a video camera for generating a local video signal. A handheld memory stores at least one handheld application that includes a video application. A handheld processing module, coupled to the handheld memory, executes the video application, based on the local video signal. A network interface sends the local video signal to a remote device via a network. A physical docking interface accesses at least one resource of an extended computer unit in a physical docked mode when the handheld computing unit is coupled to the extended computer unit via the physical docking interface. A quasi docking interface accesses at least one resource of the extended computer unit in the quasi docked mode when the handheld computing unit is coupled to the extended computer unit via the quasi docking interface.

Abstract: Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.

Abstract: A method and apparatus for processing long term orbit data that is valid for an extended period of time into the future (i.e., long term orbit data). The long term orbit data is processed by reducing redundant information from the data to form compressed long term orbit data.

Abstract: Methods and systems for processing pixels are disclosed herein. A first portion of a previously processed plurality of pixels may be buffered. A first portion of a plurality of selected pixels within a current macroblock may be filtered utilizing the buffered first portion of previously processed plurality of pixels. A second portion of the previously processed plurality of pixels may be simultaneously buffered while filtering the first portion of the plurality of selected pixels. The previously processed plurality of pixels may comprise pixels within a macroblock pair adjacent to the top of the current macroblock. The current macroblock may comprise a frame coded macroblock and/or a field coded macroblock. A second portion of the plurality of selected pixels within the current macroblock may be filtered utilizing the buffered second portion of the previously processed plurality of pixels.

Abstract: A method of playing back a television program on a playback device connected to a local area network while simultaneously storing a television program on a storage device connected to the network is disclosed. The method includes receiving a television broadcast that includes at least one program at a first settop box. A first program is stored on a permanent storage device of a network storage server connected through a network to the first settop box. While receiving the television broadcast and while storing the first program, a program is rendered on a digital media rendering device connected through the network to the first settop box.

Abstract: Aspects of a system for splicing RDMA transactions in an RDMA system may include a main processor within a main server that may receive read requests from a client device. The main processor may translate a data reference contained in each read request to generate a physical buffer list (PBL). The processor 206 may communicate the PBL to a local processor within a NIC. The local processor may utilize the PBL perform RDMA operations to retrieve data stripes contained in one or more DDP segments received from a plurality of auxiliary servers. The local processor may enable the generation of TCP packets each containing the data stripes, which may then be sent to the client. The retrieval of DDP segments and generation of TCP packets may occur within the NIC without transferring retrieved data stripes via a system bus within the main server.

Abstract: Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.

Abstract: Aspects of a method and system for network communications via a configurable multi-use Ethernet PHY are provided. In this regard, an Ethernet PHY may be configured based on characteristics of a network link over which the Ethernet PHY communicates, and a rate at which data is conveyed from a MAC to the Ethernet PHY may be controlled via a carrier sense signal of the MII. The carrier sense signal may be controlled based on a rate at which the Ethernet PHY transmits data over the network link. The Ethernet PHY may be configured based on a length of the network link and/or on a grade of the network link, where exemplary grades may comprise Cat-1 through Cat-7a cable. The Ethernet PHY may be configured into one of a plurality of modes comprising an Ethernet over digital subscriber line (DSL) mode, an extended reach mode, and a standard Ethernet mode.

Abstract: A programmable gain amplifier comprising alternatively selectable parallel circuits in a front end and independently selectable serial amplification circuits in a back end. The front end may include, for example, a plurality of transconductors in parallel and each configured to generate a current proportional to a received voltage. A ratio of the generated current to the received voltage being different for each of the transconductors. The back end is configured to receive an output of a selected member of the parallel circuits and may include a plurality of current or voltage mode amplifiers in series. For example, the back end may include a plurality of current-mode gain stages and switches configured to control which of the current-mode gain stages are used to amplify the output of the front end. The programmable gain amplifier may be used between a signal receiver and an analog to digital converter.

Abstract: Certain aspects of a method and system for dynamically adjusting forward error correction (FEC) rate to adapt for time varying network impairments in video streaming applications over IP networks may be disclosed. At a server side of a client-server communication system, a rate of transmission of forward error correction (FEC) packets to one or more clients may be dynamically adjusted based on receiving at least one upstream FEC packet from a plurality of clients. The rate of transmission of the FEC packets to the plurality of clients may be increased when a rate of occurrence of lost data packets is above a particular threshold value. The upstream FEC packets may comprise an urgent packet requesting transmission of a particular FEC packet in order to recover one or more particular lost data packets.

Abstract: Aspects of a method and system for an alternating delta quantizer for limited feedback MIMO pre-coders may comprise quantizing a change in channel state information in a MIMO pre-coding system onto at least a first and a second codebook, each of which comprises one or more unitary matrices, using a cost function; feeding back, in an alternating manner, an index to an element of at least the first codebook or the second codebook, associated with the quantizing, from a receiver to a transmitter in said MIMO pre-coding system, and generating the at least first and second codebook based on at least the channel state information. The channel state information may be a matrix V and the cost function may be defined by the following relationship: f ? ( A ) = ( 1 N ? ? j = 1 N ? ? a jj ? 2 ) where A is a matrix of size N by N and aij is element (i,j) of matrix A.

Abstract: According to one embodiment, a method for selective gate halo implantation includes forming at least one gate having a first orientation and at least one gate having a second orientation over a substrate. The method further includes performing a halo implant over the substrate. The first orientation allows a halo implanted area to be formed under the at least one gate having the first orientation and the second orientation prevents a halo implanted area from forming under the at least one gate having the second orientation. The halo implant is performed without forming a mask over the at least one gate having the first orientation or the at least one gate having the second orientation. The at least one gate having the first orientation can be used in a low voltage region of a substrate, while the at least one gate having the second orientation can be used in a high voltage region.

Abstract: A method of parameter estimation in a shared channel communications system includes the steps of receiving a preamble including a first sequence corresponding to a sequence having zero autocorrelation, a second sequence having zero autocorrelation, and a third sequence having zero autocorrelation, performing a coarse carrier frequency estimate based on the first sequence, and performing a fine carrier frequency estimate based on the second and third sequences.

Abstract: Methods, systems, and apparatuses for an integrated circuit package assembly process are provided. A wafer is received having a surface defined by a plurality of integrated circuit regions. Electrical conductors are accessible through corresponding first openings in a first passivation layer on the surface of the wafer. Solderable metal layer features are formed on the electrical conductors through the first openings. The wafer is singulated to form a plurality of flip chip dies. A plurality of package substrates is received. Each package substrate has a plurality of solder on pad (SOP) features on a respective surface. Each flip chip die is mounted to a corresponding package substrate such that each SOP feature is coupled to a corresponding solderable metal layer feature, to form a plurality of integrated circuit packages.

Abstract: A method and apparatus are disclosed for performing sampling rate conversion of an audio signal from a first sampling rate to any of a plurality of higher sampling rates using a single set of low-pass filter coefficients. Sampling rate conversion is accomplished by effectively up-sampling, low-pass filtering, and down-sampling the audio signal to generate interpolated output samples of a second digital audio signal at any of a plurality of sampling rates. The sampling rate conversion process includes storing a fixed set of filter coefficients as a plurality of phased subsets of filter coefficients, applying samples of the audio signal to the phased subsets in a rotational manner to generate filtered samples of the audio signal, and selecting and linear interpolating between certain filtered samples to generate samples of the second digital audio signal.

Abstract: Systems and methods for optimizing operation of a transceiver device are disclosed. The method may include parallel processing an input signal through a first path having a first frequency response and a second path having a second frequency response. The second frequency response may be higher than the first frequency response. Signals from the first and second paths may be combined, creating an output signal having a desired gain and frequency. The parallel processing may adjust a gain of at least one of the first path and the second path. The parallel processing may equalize at least one of the first frequency response and the second frequency response. The input signal may be from a 10 GBit Ethernet channel and/or a Fibre channel.

Abstract: A circuit includes a first wireless interface circuit that transceives packetized data between a host module and a first external device in accordance with a first wireless communication protocol. A second wireless interface circuit transceives packetized data between the host module and a second external device in accordance with a second wireless communication protocol. The second wireless interface circuit includes at least one module that is shared with first wireless interface circuit. The first wireless interface circuit and the second wireless interface circuit operate in accordance with a wireless interface schedule that includes a first time interval where the first wireless interface device and the second wireless interface device contemporaneously use the at least one module.