Abstract: Presented herein are system(s), and method(s) for non-linear scaling of source pictures to a destination screen. In one embodiment, there is presented a monitor for displaying a source picture. The monitor comprises a screen and a circuit. The screen comprises a plurality of columns, including at least one center column, a plurality of left columns, and a plurality of right columns. The circuit provides pixels for display at each of the plurality of columns of a source picture that are indicated by the phase accumulator. The phase accumulator is incremented by step values that are continuous with respect to the plurality of columns.

Abstract: A multimode communication device with a shared signal path programmable filter and a method for utilizing a shared signal path programmable filter in a multimode communication device. Various aspects of the present invention comprise a first module adapted to receive a first communication signal (e.g., corresponding to a first communication protocol) and a second module adapted to receive a second communication signal (e.g., corresponding to a second communication protocol). A shared filter, communicatively coupled to the first and second modules, may be adapted to filter the first and/or second communication signals in accordance with a plurality of selectable sets of filter response characteristics (e.g., associated with the first and second communication protocols). A filter control module may be adapted to select a set of filter response characteristics from a plurality of such sets and program the shared filter to filter a communication signal in accordance with the selected set.

Abstract: A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semiconductor device where the second substrate is formed on the first substrate; the third substrate is formed on the second substrate; and the metal element is formed on the third substrate. The second substrate is electrically grounded and is highly doped with acceptor dopant as compared to the first substrate. In this way, the second resistivity is lower than the first resistivity.

Abstract: Methods, systems, and apparatuses for synchronizing one or more output/sink devices are described. In each sink device, a communication packet is received from a source device. The communication packet includes data and a source clock timestamp. A local clock signal is generated that is synchronized with a source clock signal of the source device. The data is decoded using a codec. At least one delay and the source clock timestamp are subtracted from a current value of the local clock signal to generate a local latency value. A difference between a desired latency value and the local latency value is determined. A rate of a clock signal of the codec is adjusted according to the determined difference. Because each sink device adjusts its latency to a common desired latency value, the sink devices are thereby synchronized.

Abstract: Systems and methods for preventing damage to a unit with preventive structures are presented. In an embodiment, a unit of a collection of units includes a functional area and a preventive structure configured to prevent cracks from propagating into the functional area.

Abstract: Certain aspects of a method and system for a hardware-based implementation of USB 1.1 over a high-speed link may comprise translating at a client side of a client server communication system, USB protocol messages comprising a first USB standard to corresponding encapsulated USB protocol messages, wherein the USB protocol messages comprising the first USB standard are received from a client device at the client side of the client server communication system. The translated corresponding encapsulated USB protocol messages may be communicated from the client side to a server at a server side of the client server communication system.

Abstract: Methods and systems for detecting, and controlling power for, an auxiliary microphone are disclosed. Aspects of one method may include a detection block intermittently enabling a bias circuit block to provide a bias signal to determine if an auxiliary microphone may be communicatively coupled to a mobile device. The detection block may process 1-bit digital samples received from the bias circuit bock to determine whether the auxiliary microphone may be communicatively coupled. The detection block may also process the 1-bit digital samples to determine if a button associated with the auxiliary microphone may have been pushed or activated.

Abstract: A method and system for calibrating a plurality of modules in a communication system is provided. The method may include selecting a plurality of modules with at least one output signal and calibrating an amplitude of each selected module to be within a specified range if the amplitude is out of the specified range via a gain control processing circuit of the selected module, wherein the plurality of modules may be calibrated in an order starting with a first module located at an input of a signal path and ending with a module located at an output of the signal path. The DC component and amplitude of the envelope of the output signal may be detected by circuitry within the selected module. Muxes may be utilized to route the DC component and amplitude of the envelope to a feedback control processing circuit.

Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.

Abstract: Embodiments extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements. Accordingly, embodiments significantly reduce area requirements and control circuitry complexity of memory elements. Embodiments can be used in non-volatile memory storage, for example, and are suitable for use in system on chip (SoC) products.

Abstract: A wireless local area network (WLAN) transmitter includes a baseband processing module and a plurality of radio frequency (RF) transmitters. The processing module selects one of a plurality of modes of operation based on a mode selection signal. The processing module determines a number of transmit streams based on the mode selection signal. The processing of the data further continues by converting encoded data into streams of symbols in accordance with the number of transmit streams and the mode selection signal. A number of the plurality of RF transmitters are enabled based on the mode selection signal to convert a corresponding one of the streams of symbols into a corresponding RF signal such that a corresponding number of RF signals is produced.

Abstract: Disclosed is a closed-loop class-D amplifier circuit including a modulated reference signal generator that provides a modulated reference signal in a feed-forward path, where the reference signal is modulated corresponding to an input signal. The closed-loop class-D amplifier circuit further includes a comparator to generate a control signal based on a comparison of the modulated reference signal and a correction signal, which in turn is produced by filtering a combination of the input signal and a feedback signal. The closed-loop class-D amplifier circuit also includes a pulse generator to generate a pulse-width-modulated signal to drive an output stage of the closed-loop class-D amplifier based on the control signal.

Abstract: A network controller may split, via a pass-through driver, processing of transmit and/or receive network traffic handled by the network controller. Physical layer (PHY) processing and/or Medium Access Control (MAC) processing of the management traffic may be performed internally via the network controller. The pass-through driver may route at least a portion of management traffic carried via the transmit and/or receive network traffic externally to said network controller for processing. In this regard, the pass-through driver may enable routing of data and/or messages to enable performing the external processing of management traffic. An application processor may be used to perform the external processing of management traffic.

Abstract: Embodiments of a multi-band voltage controlled oscillator (VCO) are provided herein. The multi-band VCO is configured to adjust a frequency of an output signal based on an input signal. The multi-band VCO includes a tank module, an active module, and a control module. The tank module includes a parallel combination of a capacitor and an inductor. The active module includes a pair of cross-coupled transistors that are configured to provide a negative conductance that cancels out a positive conductance associated with the tank module. To improve the phase noise associated with the multi-band VCO, the control module is configured to adjust the body voltage of the cross-coupled transistors.

Abstract: A method and system are provided for providing data commonality in a programmable transport demultiplexer engine. The method may involve utilizing a hardware assist block to process a portion of an incoming data packet, which may result in a partially processed data packet. The data packet may comprise data in any one of video formats and/or audio formats. A firmware block may then execute a plurality of instructions to process the partially processed data packet. The plurality of instructions may be independent of video and/or audio formats associated with the data packet.

Abstract: In a RF communications system, aspects for implementing a single weight single channel MIMO system with no insertion loss may comprise generating at least one control signal that is utilized to control at least one of a plurality of received signals in a WCDMA and/or HSDPA system. A phase of a first of the plurality of received signals may be adjusted outside of a first processing path used to process that signal so that it is equivalent to a phase of at least a second of the plurality of received signals. A gain in the first processing path may be equivalent to a gain in a second processing path that is utilized to process the second of the plurality of received signals. The control signal may be utilized to adjust a phase and/or an amplitude of at least one of a plurality of received signals.

Abstract: A method and related computer program product for combining resources of multiple RAID controllers and managing them as a single entity, comprising searching the RAID controllers for the most appropriate version of the firmware to be executed, determining whether a more appropriate version of the firmware was previously loaded into system memory, unloading inappropriate versions of the firmware, loading the most appropriate version of the firmware and initializing all RAID controllers as a commonly managed entity having combined resources.

Abstract: A method, apparatus and computer program product for generating and processing upstream channel descriptor (UCD) messages in a DOCSIS-based broadband communications system, such as a DOCSIS-based two-way satellite communications system, is provided. A satellite modem termination system (SMTS) generates a UCD message that includes one or more standard parameters pertaining to an upstream channel of the two-way satellite communications system, wherein the one or more standard parameters are defined in accordance with the DOCSIS protocol, and one or more satellite application-specific parameters pertaining to the upstream channel, wherein the one or more satellite application specific parameters are not provided for by the DOCSIS protocol. The UCD message is transmitted to a satellite modem that extracts both the standard and satellite application-specific parameters for use in managing communication over the upstream channel.

Abstract: Flesh-tones corrections may be performed to correct color shifts that may occur in transmitted video frames wherein chroma information corresponding to flesh-tone video pixels may be distorted. A target region may be determined based on a determined flesh-tones region within a spatial representation of chroma in video color space, such as Y?CrCb. The flesh-tones correction may utilize one or more methodologies based on an elliptical shape and/or a triangular shape algorithm(s). A video processing system may be utilized to analyze chroma information of received video pixels and/or to perform flesh-tones corrections by shifting the chroma value of received video pixels towards good flesh-tones regions to compensate for possible distortions. The video processing system may perform conversion calculation and/or shift operations dynamically. The video processing system may also utilize lookup tables (LUTs) to convert received chroma values.

Abstract: Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp.