Abstract: A digital-to-analog conversion circuit operates by selectively discharging members of a plurality of capacitors. Charging of the capacitors occurs during a reset period while digital-to-analog conversion occurs as the capacitors are discharged. Those capacitors that are discharged are selected from the plurality of capacitors based on a digital input. The analog output includes the charge discharged from the capacitors. The capacitors are optionally divided into separate capacitor banks.

Abstract: Methods and systems for mosaic mode display of video are disclosed. Aspects of one method may include generating video data for a plurality of video windows using a single video feeder module comprising a single video scaler and a single video capture module. The video data for the video windows may be generated in a single frame time. Register DMA may be used to transfer register update data (RUD) to a plurality of registers to configure video processing for generating video data for a video window. The plurality of RUDs may be generated in response to a single interrupt to a processor, and may be configured as a linked list or stored sequentially in memory. The configuring may occur prior to generating video data for the corresponding video window. Video processing for a subsequent video window may be configured automatically after generating video data for the present video window.

Abstract: A system and method for providing an interface an interface between a read channel and a disk controller. The interface includes a plurality of differential pair signal lines operable to communicate data and control signals between the read channel and the hard disk controller. The data and control signal lines communicate operations for transferring data between the disk controller and the read channel.

Abstract: Selective fast image rejection. Selective down conversion processing is performed on a received signal based on the signal strength of that received signal. As few as two possible down conversion frequencies can be employed so that the received signal is down converted either to a first down converted signal having a first intermediate frequency or to a second down converted signal having a second intermediate frequency. If desired, the received signal can either be down converted using low side injection or high side injection down conversion processing. Alternatively, a larger number of possible down conversion frequencies so that the received signal is down converted to one of the possible down conversion frequencies based on the signal strength of the received signal.

Abstract: Embodiments of a flash analog-to-digital converter (ADC) that can detect and suppress bubbles in a thermometer code of a flash ADC are provided herein. Bubbles can result in large sparkle errors, which degrade the bit error rates (BER) of flash ADCs. The present invention utilizes a bubble correction module that is configured to provide a bubble corrected one-of-N code by suppressing at least one of any two tops that are not separated by at least two levels within a one-of-N code.

Abstract: A self servo writing disk controller detects a plurality of spiral sync marks and a plurality of spiral bursts corresponding to one of a plurality of servo spirals from a read signal from the read/write head. A timing reference signal is generated based on timing of at least one of the plurality of the spiral sync marks. A position error signal is generated based on timing of at least one of the plurality of spiral sync marks and a magnitude of at least one of a plurality of spiral bursts. The timing reference signal and the position error signal are used by the disk drive for timing and positioning in self writing initial servo wedges to the disk.

Abstract: Aspects of a method and system for an integrated antenna and antenna management are provided. In this regard, one or more reactances coupled to an antenna in a hybrid circuit may be tuned and signals may be transmitted and/or received based on the tuning. The hybrid circuit may comprise an integrated circuit (IC) bonded to a multi-layer package. The antenna may be embedded within and/or on the multi-layer package. The reactances may be within and/or on the IC and/or the multi-layer package. In this regard, the IC may be bonded to or mounted to an underside of the multi-layer package. The reactances may be tuned via one or more switching elements and/or logic, circuitry, and/or code within the IC. The reactances may comprise one or more inductors and/or capacitor arrays. The multi-layer package may comprise one or more layers of ferromagnetic and/or ferrimagnetic material.

Abstract: A technique to remove second order and third order nonlinearity distortions caused by a blocker signal at an input of a radio receiver. An envelope detector is utilized at an input of the RF front-end of the receiver to obtain a magnitude of the overall signal. The output of the envelope detector is then processed at baseband to estimate coefficients that relate to the distortion. Once the coefficients are obtained, the coefficients are applied at an I/Q imbalance correction stage to also correct for the distortion by cancelling the distortion from the received signal.

Abstract: According to one embodiment, a compact low-power receiver comprises a front-end producing a front-end gain and a back-end producing a back-end gain. The front-end includes a transconductance amplifier providing digital gain control and outputting an amplified receive signal, a mixer for generating a down-converted signal from the amplified receive signal, and a transimpedance amplifier (TIA) including a current mode buffer. The TIA provides gain control for amplifying the down-converted signal to produce a front-end output signal. In one embodiment, the back end includes a second-order low-pass filter to produce a filtered signal from the front-end output signal and an analog-to-digital converter (ADC), wherein the filtered signal is fed directly to the ADC without direct-current (DC) offset cancellation being performed. In various embodiments, the front-end gain is substantially greater than the back-end gain.

Abstract: According to one embodiment, a concurrent impedance and noise matching transconductance amplifier designed for implementation in a receiver comprises an input device configured to couple to a matching network of the receiver, and a boost capacitor connected to the input device to increase an input capacitance of the transconductance amplifier. The boost capacitor is selected to substantially minimize the receiver noise and to enable the concurrent impedance and noise matching of the receiver and the matching network. In one embodiment, the receiver comprises the transconductance amplifier to provide an amplified receive signal, and a mixer to produce a down-converted signal corresponding to the amplified receive signal, wherein the mixer is coupled to the transconductance amplifier by a blocking capacitor. The blocking capacitor is selected to substantially increase an amplitude ratio of the down-converted signal to the amplified receive signal to substantially increase the front-end gain of the receiver.

Abstract: Embodiments of a method and system for supporting co-existence of first and second cellular networks in adjacent channels in the same geographical area are provided. The method and system synchronize the two cellular networks such that their respective uplink transmissions are aligned in time and their respective downlink transmissions are aligned in time. Such synchronization prevents (or substantially prevents) the uplink transmissions from one of the two cellular networks from overlapping with the downlink transmissions of the other cellular network, and vice versa, thereby mitigating interference between the two networks.

Abstract: According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Abstract: A system includes a mobile device providing a plurality of applications and an agent providing first and second authentication procedures for authenticating a user of the mobile device to first and second applications running on the mobile device. A first application is enabled by authenticating a user through a first authentication procedure, and a second application is enabled by authenticating a user through a second authentication procedure. The agent authenticates the user to the first application following the first authentication procedure, and the agent authenticates the user to the second application following the second authentication procedure.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A method of handling datagrams in a network device coupled to other network devices is disclosed. The method includes the steps of receiving an incoming datagram at a port of the network device, determining an egress port for the incoming datagram based on a destination address contained in the incoming datagram and a lookup of an address resolution lookup (ARL) table and performing a lookup of the ARL table based on a source address contained in the incoming datagram to determine whether the source address has been learned previously. The method also includes the steps of writing an entry into the ARL table when the source address has not been learned previously, determining whether the other network devices have learned the source address when the source address has been learned previously and continuing to relay a learning message with the source address to the other network devices when it is determined that the other network devices have not learned the source address.

Abstract: An integrated circuit includes a substrate. A first integrated circuit die includes a first circuit and a first intra-chip clock interface that transmits a first clock signal via the substrate. A second integrated circuit die includes a second circuit that operates based on the first clock signal and a second intra-chip clock interface that recovers the first clock signal from the substrate.

Abstract: A method for processing network information in a multi-server platform is disclosed and includes receiving by a blade server manager, capacity utilization information embedded in spare link bandwidth from a plurality of blade servers operably coupled to the blade server manager. Digital information received on a digital communication link may be forwarded to one of the plurality of blade servers. The blade servers may be selected based on the received capacity utilization information. The capacity utilization information may include blade server work load capacity, blade server power saving capacity, blade server CPU percent utilization, and/or data representing blade server interrupt utilization. The blade server manager may be operably coupled to an Ethernet network and/or an external network.

Abstract: A method and an apparatus for efficient Gold code generation and management in WCDMA systems are presented. Aspects of the method may include simultaneously generating, based on the codeword sequence, a plurality of scrambling code segments associated with a scrambling code. A plurality of scrambling code segments, where each is associated with a corresponding one of a plurality of scrambling codes, may also be simultaneously generated. The plurality of scrambling codes may form a scrambling code group. Based on the codeword sequence, a plurality of time shifted versions of at least one scrambling code segment associated with a scrambling code may also be simultaneously generated.

Abstract: Switching between communication ports of a notebook is typically accomplished using an off-chip local area network (LAN) switch or an off-chip high speed analog multiplexer. This off-chip component is disadvantageous for several reasons, including: added cost of an additional component; increased overall power consumption because transmit amplitude loss; and reduced cable reach and link performance due to hybrid mismatch and signal distortions. To reduce cost and preserve electrical and networking performance, an integrated switch is provided to multiplex signals of a networking communication chip to multiple network paths.

Abstract: Aspects of the present invention may be found in a method and system for cellular network services and an integrated broadcast television (TV) downlink having intelligent service control with feedback information. The system may comprise cellular processing circuitry in a mobile terminal that processes a plurality of cellular frequency band communications services which comprise at least one voice service and at least one data service, in a single cellular processor integrated circuit in a mobile terminal. In addition, the system may comprise broadcast processing circuitry in the mobile terminal that processes VHF/UHF band broadcast services in a single broadcast processor integrated circuit in the mobile terminal. The cellular processing circuitry may communicate with, and share at least a single memory with, the broadcast processing circuitry.