Abstract: Packet loss concealment (PLC) systems and methods are described that use time-warping to merge a concealment signal generated to replace one or more bad frames of an audio signal with a received signal representing one or more subsequent good frames of the audio signal in a manner that avoids signal discontinuity and audible artifacts resulting therefrom. Prediction-based PLC systems and methods are also described that use time-warping to conceal the loss of one or more frames containing a transition region in a manner that will not result in an audible artifact.

Abstract: Disclosed is a power-efficient multi-mode charge pump. The charge pump comprises a first pumping circuit that provides at least one output voltage produced by a discharge sequence of a shared flyback capacitor. The charge pump also comprises a second pumping circuit that provides a plurality of output voltages produced by a corresponding plurality of discharge sequences of the shared flyback capacitor. The charge pump may include a transition circuit to selectably enable the first pumping circuit or the second pumping circuit. In one embodiment, the first pumping circuit may employ a two-phase discharge sequence. In another embodiment, the second pumping circuit may employ a three-phase plurality of discharge sequences. A related method is also disclosed.

Abstract: Disclosed is a false-link protection circuit comprising at least one native switch coupled between a communication terminal of a first differential switch and a communication terminal of a second differential switch. The at least one native switch is configured to provide an attenuation path for a pulse link signal received by either communication terminal when the first and second differential switches are in a powered down state. According to one embodiment, a method to attenuate a pulse link signal comprises activating a native switch of a false-link protection circuit by powering down first and second differential switches, receiving a pulse link signal at a communication terminal of one of the first and second differential switches, and attenuating the pulse link signal by diverting it through the false-link protection circuit when the first and second differential switches are in a powered down state.

Abstract: A noise cancellation system has a first transformer with an input side and an output side, the input side having first and second taps coupled to a signal provider, and a center tap providing a first common-mode voltage signal. A first digital subscriber line (xDSL) modem has an input coupled to the output side of the first transformer and an output coupled to customer premises equipment (CPE) for providing an xDSL signal to the CPE. A second transformer has an input side and an output side, the input side having first and second taps coupled to a signal provider, and a center tap providing a second common-mode voltage signal. A second xDSL modem is coupled to the output side of the second transformer. The difference between the first and second common-mode voltage signals is provided to at least one of the first and second xDSL modems to flier out noise from the xDSL signal provided by that modem.

Abstract: A transmitter includes a detection element to determine when a current power requirement of a communication link is less than the standard transmit power. The current power requirement may be determined by a current operation condition of the communication link, for instance. The transmit power of the transmitter may be set to be less than the standard power in any of a variety of ways. For example, a center tap voltage of the transmitter may be reduced. In another example, a class of operation of the transmitter may be changed. In yet another example, the transmitter may include a current mirror having a plurality of diode-connected transistors coupled in parallel, thereby reducing the current at output terminals of the transmitter. Reducing the current at the output terminals decreases the output power of the transmitter, which may reduce the power consumed by the transmitter.

Abstract: Systems and methods of coding progressive content with isolated fields for conversion to interlaced display are provided. Some systems and methods may find use in, for example, digital video compression systems and methods. Film material may be encoded as video material with an intended field polarity and an explicit 3:2 pull-down operation for interlaced display (e.g., a 30-frames-per-second display).

Abstract: Disclosed is an inrush current control circuit for controlling current into a high-current circuit block. The inrush current control circuit comprises a number of distributed switches and a digital control circuit coupled to at least one of the distributed switches. The digital control circuit is configured to switch a first group of the distributed switches in response to an enable/disable signal. The digital control circuit is further configured to switch a second group of the distributed switches after a first programmable delay. According to one embodiment, a method comprises switching a first group of distributed switches by a digital control circuit of an inrush current control circuit in response to an enable/disable signal, and switching a second group of the distributed switches by the digital control circuit after a first programmable delay, thereby resulting in regulation of a flow of an inrush current.

Abstract: Low complexity error correction using cyclic redundancy check (CRC). Communications between at communication devices, sometimes including at least one redundant transmission from a transmitter to a receiver, undergo low complexity error correction. CRC may be employed in conjunction with using any desired type of ECC or using uncoded modulation. Based on CRC determined bit-errors, as few as a singular syndrome associated with a singular bit-error or a linear combination of syndromes associated with two or more singular bit-errors within two or more received signal sequences are employed to perform error correction of the received signal. Real time combinations of multiple syndromes associated with respective single bit-errors (that may themselves be calculated off-line) are employed in accordance with error correction. In addition to CRC, any ECC may be employed including convolutional code, RS code, turbo code, TCM code, TTCM code, LDPC code, or BCH code.

Abstract: An integrated circuit may enable transmission and reception of Bluetooth signals as well as FM signals. One or more clock signals may be generated via a phase-locked loop and may be utilized to enable Bluetooth transmission and reception. Bluetooth clock signals and frequency control words may be utilized by a direct digital frequency synthesizer to generate FM carrier signals that enable FM reception as well as digitally modulated signals for FM transmission. FM reception and transmission may be time division duplex. Frequency control words may be adjusted to compensate for variations in the Bluetooth clock signal frequency for FM carrier signals used in FM reception. Moreover, frequency control words may be adjusted to modulate a signal about the frequency of an FM carrier for transmission. Each of the Bluetooth clock signals, carrier signals and modulated signals comprise an in-phase component and a quadrature-phase component.

Abstract: A network device for implementing mirroring on packets. The network device includes a plurality of ports, each of which is at least one of an ingress port, an egress port and a mirror-to port. The network device also includes processing means for supporting a plurality of mirroring types. Each of the ingress port, egress port and mirror-to port includes at least one register for supporting the plurality of mirroring types. To support mirroring at each of the ingress port, egress port and mirror-to port predefined bits in the at least one register are set. When an incoming packet is received, the predefined bits are examined to determine which of the plurality of mirroring types to apply to the packet.

Abstract: A method and apparatus for providing a dual-loop phase lock loop (PLL) for a radio-frequency (RF) receiver is provided. The dual-loop PLL may include coarse tuning circuitry and fine tuning circuitry. The coarse turning circuitry and fine tuning circuitry may be arranged in parallel. Both of the coarse tuning circuitry and fine tuning circuitry provide respective tuning signals to a voltage-controlled oscillator (e.g., a varactor tuned VCO). The coarse tuning circuitry and the fine tuning circuitry may provide the respective tuning signals simultaneously. In addition, coarse and fine tuning circuitry may be formed monolithically with other elements of the dual-loop PLL so as to provide a highly-integratable having a wide frequency lock range and high sensitivity.

Abstract: A system and method of supporting controlled access to multimedia information and media-related services via a broadband access gateway is disclosed. A plurality of user manageable tiers of access privilege may be implemented by the broadband access gateway, that may support communication using, for example, a wireless personal area network and a broadband network. A different degree of user authentication and/or identification may be established for each of the tiers, and users may be restricted in their access to multimedia information and services by their current tier of access privilege. The multimedia information and services may be provided by a variety of access devices via the personal area network, and from providers accessible via the broadband network connected to the gateway. Examples of access devices include mobile multimedia handsets, personal digital assistants, personal computers, digital cameras, and printers.

Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel.

Abstract: Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry.

Abstract: A method and apparatus for estimating a satellite signal parameter in a satellite positioning system receiver is described. In an example, a plurality of correlation results between a satellite signal and a reference signal is generated in response to a command from a processor. At least one satellite signal parameter is estimated from the plurality of correlation results using a co-processor integrated within the satellite positioning system receiver. The at least one satellite signal parameter is then provided to the processor.

Abstract: A method and system for reducing the appearance of jaggies when deinterlacing moving edges in a video processing system are provided. The method may comprise detecting the direction of an angled edge in an interlaced video image to determine a filtering direction to be used for approximating absent pixels in deinterlacing the interlaced video. In detecting the direction of the angled edge, a group of windows of different sizes may be used to look at the edge, where a missing pixel is the center of each of the windows. Detecting the direction of the edge, and therefore the direction of filtering, may comprise: determining the angle associated with the edge, determining the strength of the edge, examining the pixels surrounding the absent pixel, and adjusting the first angle measure and the second angle measure based on the pattern of the surrounding pixels.

Abstract: An integrated circuit (IC) includes a first die, a second die, a packaging substrate, and coupling circuit. The first die includes first circuitry and the second die includes second circuitry. The packaging substrate supports the first and second dies, wherein the first and second dies are stacked with respect to the packaging substrate. The coupling circuit couples the first die to the second die, wherein the first and second circuitry communicate via the coupling circuit.

Abstract: A technique is described herein for updating a state of a decoder configured to decode a series of frames representing an encoded audio signal. In accordance with the technique, an output audio signal associated with a lost frame in the series of frames is synthesized. The decoder state is set to align with the synthesized output audio signal at a frame boundary. An extrapolated signal is generated based on the synthesized output audio signal. A time lag is calculated between the extrapolated signal and a decoded audio signal associated with a first received frame after the lost frame in the series of frames, wherein the time lag represents a phase difference between the extrapolated signal and the decoded audio signal. The decoder state is then reset based on the time lag.

Abstract: A video processing system may implement a video scaling algorithm using interpolation based on polyphase filtering. A video or graphics scaler may be utilized to scale luma, chroma, and/or alpha information in a video image. The scaler may comprise a first polyphase sub-filtering with zero phase shift that generates an in-phase filtered output from an input video image and a second polyphase sub-filtering that generates an out-of-phase filtered output from the input video image. The video scaler may also comprise an interpolator that may generate a scaled video image based on the generated in-phase and out-of-phase filtered outputs and a scaling factor. The scaling factor may be determined based on an input video size (M) and a desired output video size (N). The interpolation of the generated in-phase and out-of-phase filtered outputs in the video scaler may be implemented by utilizing a Farrow structure.

Abstract: A radio transceiver device includes circuitry for radiating electromagnetic signals at a very high radio frequency both through space, as well as through wave guides that are formed within a substrate material. In one embodiment, the substrate comprises a dielectric substrate formed within a board, for example, a printed circuit board. In another embodiment of the invention, the wave guide is formed within a die of an integrated circuit radio transceiver. A plurality of transceivers with different functionality is defined. Substrate transceivers are operable to transmit through the wave guides, while local transceivers are operable to produce very short range wireless transmissions through space. A third and final transceiver is a typical wireless transceiver for communication with remote (non-local to the device) transceivers. Additionally, a multi-mode transceiver is operable to configure transmit and receive circuitry based upon transmission path.