Abstract: Aspects of a method and system for SFBC/STBC transmission of orthogonally coded signals with angle feedback in a diversity transmission system are presented. Exemplary aspects of the system may include one or more circuits that enables generation of a plurality of concurrently transmitted signal groups based on a computed matrix such that a product of the plurality of concurrently transmitted signal groups, the computed matrix and/or a transformed version of the computed matrix, may generate at least one set of orthogonal signals based on at least one rotation angle.

Abstract: Aspects of a method and system for channel estimation in a SM MIMO communication system may comprise receiving a plurality of spatially multiplexed communication signals from a plurality of transmit antennas. A plurality of baseband combined channel estimates based on phase rotation may be generated in response to the received plurality of spatially multiplexed communication signals. An estimate of the channel matrix may be determined based on the baseband combined channel estimates. A plurality of amplitude and phase correction signals may be generated in response to receiving the estimate of the channel matrix. An amplitude and a phase of at least a portion of the received plurality of spatially multiplexed communication signals may be adjusted based on the generated plurality of amplitude and phase correction signals, respectively.

Abstract: The present invention describes a communications system having a first link partner and a second link partner that are connected by a communications link having at least four pairs of conductors. According to IEEE Standard 802.3 (e.g. Ethernet) for 1000Base-T, a data link is maintained (in a period absent data transmission) by sending idle signals over four pairs of conductors of the cable to maintain a logical connection. This idle signal scheme is replaced with an alternate idle signaling scheme that uses only two pairs of conductors to maintain a logical connection and therefore can operate with using lower power. The other two pairs of conductors of the four pairs of conductors are unused to maintain a logical connection absent data transfer, and therefore can be used to implement a Suspend Mode of operation. During Suspend Mode, the physical layer of each link partner powers down unnecessary circuitry so as to operate in a low power environment.

Abstract: A technique is provided for automatically adjusting the volume, or magnitude, of an audio signal. The technique includes calculating an average power associated with a segment of an input audio signal, determining whether the average power is greater than an estimated signal level associated with one or more previously-processed segments of the input audio signal and, depending on the determination, either calculating an updated estimated signal level by subtracting from the average power an attenuated difference between the estimated signal level and the average power or setting the updated estimated signal level to the average power. A gain to be applied to the segment of the input audio signal is then determined based on the updated estimated signal level and a target signal level for an output audio signal.

Abstract: Certain embodiments of the invention may be found in a method and system for performing SCSI read operations with a CRC via a TCP offload engine. Aspects of the method may comprise receiving an iSCSI read command from an initiator. Data may be fetched from a buffer based on the received iSCSI read command. The fetched data may be zero copied from the buffer to the initiator and a TCP sequence may be retransmitted to the initiator. A digest value may be calculated, which may be communicated to the initiator. An accumulated digest value stored in a temporary buffer may be utilized to calculate a final digest value, if the buffer is posted. The retransmitted TCP sequence may be processed and the fetched data may be zero copied into an iSCSI buffer, if the buffer is posted. The calculated final digest value may be communicated to the initiator.

Abstract: Methods and systems for clocking FM transmit, FM receive and near field communication functions using DDFS are disclosed. Aspects of one method may include generating a Bluetooth signal that may comprise, for example, I and Q components, or Bluetooth local oscillator (LO) signals, for use in Bluetooth communication. One of the two Bluetooth LO signals may then be used by a DDFS to generate I and Q LO signals for FM reception and/or transmission. One of the I and Q LO signals for FM communication may be used by another DDFS to generate at least one LO signal for near field communication (NFC) transmission and/or reception. While the Bluetooth LO signal may vary in frequency as Bluetooth frequency hopping occurs, the FM LO signals may remain constant for a specific channel frequency. Similarly, while the FM LO signals may be changed to tune to different FM channels, the NFC LO signals may remain at a constant frequency.

Abstract: A dongle transceiver a substrate, a transceiver circuit, a transmit/receive switch, a MIMO antenna structure, and a decoupling module. The transceiver circuit is on at least one of the first and second sides of the substrate and is coupled to the transmit/receive switch. The MIMO antenna structure is on at least one of the first and second sides of the substrate. The decoupling module is on at least one of the first and second sides of the substrate, couples the MIMO antenna structure to the transmit/receive switch, and electrically isolates antennas of the MIMO antenna structure.

Abstract: According to the present invention, Bluetooth master device offset information is determined and distributed among the master devices within a Bluetooth network. The system either provides an offset to each master device or determines master device offsets and distributes this information to master devices within the system to allow or efficient hand-offs of a slave between master devices.

Abstract: A technique to provide a hardware security module that provides a secure boundary for retention of a secure key within the secure boundary and prevention of unauthorized accesses from external sources outside of the secure boundary to obtain the secure key. The hardware security module includes a security processor to unwrap and authenticate a secure key within the secure boundary to decrypt or encrypt data and to provide data through a single interface that communicates with external sources, so that all data transfers between the secure boundary, formed by the hardware security module, and external sources are transferred only through the interface. The hardware security module ensures no unwrapped key leaves the secure boundary established by the hardware security module.

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract: Systems and methods that provide antenna selection in multi-antenna-element communication systems are provided. In one embodiment, a system that selects N antenna elements in an M-antenna-element transmitter or an M-antenna-element receiver, in which N is less than M, may include, for example, M antenna elements in the M-antenna-element transmitter or the M-antenna-element receiver; N RF chains; and a switch coupled to the N RF chains. The M-antenna-element receiver may determine a bit error rate for each possible N antenna element subset of the M antenna elements. The M-antenna-element receiver may determine the particular N antenna element subset with a lowest bit error rate. In response to the determination of the particular N antenna element subset with the lowest bit error rate, the switch may couple the N RF chains to the particular N antenna element subset with the lowest bit error rate.

Abstract: Smart routing between peers in a point-to-point link based system begins when a device of a plurality of devices in a point-to-point link interconnected system receives a packet from an upstream link or a downstream link. The processing continues when the device interprets the packet to determine a destination of the packet. If the device is the destination of the packet, the device accepts the packet. If, however, the device is not the destination of the packet, the device forwards the packet on another upstream link or another downstream link without alteration of at least one of: source information of the packet and destination information of the packet.

Abstract: A Wireless Access Point (WAP) of a Wireless Local Area Network (WLAN) infrastructure includes a processor, a radio and a directional antenna. The radio supports communications with a plurality of wireless terminals to gather participatory data, and listens to, but does not participate in transmissions of at least some of the plurality of wireless terminals to collect non-participatory WAP data. Based upon the participatory WAP data and non-participatory WAP data, the processor creates WAP operational reports and provides the WAP operational reports to the WLAN. The WLAN creates directions based thereon and directs the WAP to alter the gain pattern of the directional antenna.

Abstract: A technique to provide an integrated circuit that performs memory partitioning to partition a memory into a plurality of regions, in which the memory is accessed by a plurality of heterogeneous processing devices that operate to access the memory. The integrated circuit also assigns a security level for each region of the memory and permits a memory access by a transaction to a particular region of the memory, only when a level of security assigned to the transaction meets or exceeds the assigned security level for the particular region. The integrated circuit also performs sandboxing by assigning which of the plurality of processing devices are permitted access to each of the plurality of regions. The integrated circuit may implement only the security level function or only the sandboxing function, or the integrated circuit may implement them both. In some instances, a scrambling/descrambling function is included to scramble/descramble data.

Abstract: A system and method for implementing a multi-voltage multi-battery power management integrated circuit. Various aspects of the present invention provide a power management integrated circuit. The power management IC may comprise a first regulator module that receives a first battery power signal from a first battery characterized by a first battery voltage and outputs a first regulated power signal, based at least in part on the first battery power signal. The power management IC may also comprise a second regulator module that receives a second battery power signal from a second battery characterized by a second battery voltage and outputs a second regulated power signal, based at least in part on the second battery power signal. The second battery voltage may, for example, be substantially different than the first battery voltage. The power first and second regulated power signals may, for example, correspond to substantially different power supply voltages.

Abstract: According to one embodiment, a semiconductor device comprises a high-k gate dielectric overlying a well region having a first conductivity type formed in a semiconductor body, and a semiconductor gate formed on the high-k gate dielectric. The semiconductor gate is lightly doped so as to have a second conductivity type opposite the first conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise an isolation region formed in the semiconductor body between the semiconductor gate and a drain of the second conductivity type, and a drain extension well of the second conductivity type surrounding the isolation region in the semiconductor body. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including one or more CMOS logic devices.

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract: A method relating to wireless human interface device (HID) coordination is disclosed. A first human interface device (HID) is wirelessly coupled to two or more computing devices, wherein the first HID is configured to toggle between interactions with each of the two or more computing devices. An inquiry or paging message is broadcast to one or more HIDs, including a second HID wirelessly coupled to the two or more computing devices, wherein the second HID is configured to receive and provide a response to the inquiry or paging message. The second HID is located based on the response to the inquiry or paging message. A wireless link is established between the first HID and the second HID based on the identifying, wherein the first HID is configured to coordinate, via the wireless link, interactions with the two or more computing devices by both the first HID and the second HID based on the toggle.

Abstract: A single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing is provided. This processing may be divided between various processing modules. This single chip includes a processing module having an ARM microprocessor and a digital signal processor (DSP), an RF section, and an interface module. The processing module converts an outbound voice signal into an outbound voice symbol stream, converts an inbound voice symbol stream into an inbound voice signal, converts outbound data into an outbound data symbol stream, and converts an inbound data symbol stream into inbound data. These functions may be divided between the ARM microprocessor and DSP, where the DSP supports physically layer type applications and the ARM microprocessor supports higher layer applications. Further bifurcation may be based on voice applications, data applications, and/or RF control.

Abstract: Embodiments enable a multi-band transmitter with significantly reduced architecture area by allowing maximum reuse of transmitter stages across supported frequency bands and signal standards. Further, embodiments allow a monolithic transmitter implementation by providing an integration-friendly differential to single-ended conversion stage. According to embodiments, the differential to single-ended conversion stage is readily configurable according to the frequency band and signal standard of operation of the transmitter.