Abstract: Methods and systems for sample rate conversion convert a sampled signal to a higher data rate signal. Conversion pulses are received, having a conversion rate that is higher than the sample rate of the sampled signal. Sample points are then reconstructed from the sampled signal, in real time, on either side of a conversion pulse. An interpolation is performed between the reconstructed sample points, at the time of the conversion pulse. The interpolation results are outputted in real time. The process is repeated for additional conversion pulses. The outputted interpolated amplitudes form the higher data rate signal having a data rate equal to the conversion rate. Sample rate conversion is thus performed in real time according to the higher data rate clock, rather than with fixed ratios. As a result, when the higher data rate clock is affected by, for example, jitter or other frequency variations, the higher data rate samples immediately track the lower data rate samples.

Abstract: A plurality of CMTS devices are linked together and synchronized to facilitate communication between the respective CMTS devices and respective downstream cable modems. According to one embodiment of the invention, one of the CMTS devices is designated as a master device, and the other CMTS devices are designated as slave devices. The respective CMTS devices are connected to each other by means of a synchronization bus. The master CMTS device then generates and broadcasts a future time stamp value, which is received by the respective slave CMTS devices. When the time stamp counter in the master CMTS device reaches the transmitted value, a control signal is broadcast over the synchronization bus. The slave CMTS devices then retrieve the time stamp value and reset their respective local time stamp counters to the received value. In this manner, the CMTS devices are synchronized.

Abstract: A system and method for processing signals in a wireless communication system is disclosed. The method may include transmitting a wireless signal from a transmitter, and receiving at the transmitter, feedback information from a receiver that receives the transmitted wireless signal. The received feedback information may include one or more of a plurality of weight values corresponding to a maximum signal-to-interference-plus-noise ratio (SINR) value that is determined from a plurality of SINR values. The receiver may generate the plurality of SINR values from the received transmitted wireless signal based on the corresponding plurality of weight values. The feedback information that includes the one or more of the plurality of weight values may be received by the transmitter via one or more uplink communication channels. The at least one uplink communication channel may include a high-speed dedicated physical control channel (HS-DPCCH).

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Abstract: Methods and systems for audio CODEC voice ADC processing are disclosed. Aspects of one method may include using a decimating filter that may be enabled to generate 13 MHz, 9-level digital output signal from a 26 MHz, 3-level digital input signal. The 13 MHz, 9-level digital output signal may be processed for RF transmission, for audio output to an output device, and/or utilized for testing by a test fixture, for example. The 13 MHz, 9-level digital output signal may be further processed to generate a 6.5 MHz, 33-level digital signal. The 6.5 MHz, 33-level digital signal may be converted to an analog signal, and processed for audio output and/or testing. The 13 MHz, 9-level digital output signal may also be processed to generate a 40 KHz, 17-bit digital signal, which may be communicated to a test equipment or further processed for RF transmission.

Abstract: A baseband digital processing module operates cooperatively with an analog signal processing module to effectuate highly adjustable and highly accurate gain adjustment in accordance with transmitter processing within a communication device. The gain adjustment and/or gain control is partitioned between the digital and analog domains by employing two cooperatively operating digital and analog modules, respectively. Gain adjustment in the analog domain is performed in a relatively more coarse fashion that in the digital domain. If desired, gain adjustment in each of the analog and digital domains is performed across a range of discrete steps. The discrete steps in the analog domain are larger than the discrete steps in the digital domain. Also, the discrete steps in the digital domain may be interposed between two successive discrete steps in the analog domain.

Abstract: Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices).

Abstract: An integrated circuit (IC) includes a package substrate, a die, and a plurality of antenna structures. The die includes a radio frequency (RF) transceiver and a control module, wherein the RF transceiver processes inbound and outbound RF signals. The control module enables the RF transceiver to receive the inbound RF signal from one or more of the plurality of antenna structures in a frequency band of approximately 55 GHz to 64 GHz and enables the RF transceiver to provide the outbound RF signal to one or more of the plurality of antennas structures for transmission in a frequency band of approximately 55 GHz to 64 GHz.

Abstract: Provided are systems and methods for providing enhanced motion detection. One system providing enhanced motion detection includes a smart display, an interface subsystem including a human interface device (HID), and a console having a processor configured to form communication links with the smart display and the interface subsystem and to provide motion detection feedback, using the smart display, to a user of the HID, where the HID is configured to sense motion of the HID and utilize a predictive model to characterize the motion of the HID. One interface subsystem includes a camera to sense motion of a user of the HID. One processor is configured to negotiate a reduced response latency with the smart display.

Abstract: An integrated circuit for use in an RFID tag includes an integrated circuit die having a circuit, a radio frequency identification (RFID) interface for providing communication between the circuit and a remote RFID reader via RF signaling between the RFID interface and the remote RFID reader. An antenna section facilitates the RF signaling between the RFID and the remote RFID reader. A substrate is coupled to support the first integrated circuit die and at least a portion of the antenna section.

Abstract: Systems and methods that support storage device content authentication are provided. A system that verifies storage device content received from a storage device may comprise, for example, a security processor coupled to the storage device. The security processor may be adapted to receive a partitioned storage device region from the storage device. The partitioned storage device region may comprise, for example, regional content and first hashed regional content. The security processor may generate, for example, second hashed regional content by performing a hashing function on the regional content received by the security processor. The security processor may compare, for example, the first hashed regional content to the second hashed regional content. The security processor may verify the regional content received by the security processor if the first hashed regional content is the same as the second hashed regional content.

Abstract: According to one exemplary embodiment, a transmitter module includes a line drive including a current digital-to-analog converter, where the line driver provides an analog output waveform. The current digital-to-analog converter receives a digitally filtered input waveform including at least two voltage steps. The at least two voltage steps of the digitally filtered input waveform cause a rise time of the analog output waveform to have a reduced dependency on process, voltage, and temperature variations in the line driver, while meeting stringent rise time requirements. The digitally filtered input waveform has an initial voltage level and a final voltage level, where the final voltage level is substantially equal to a sum of the at least two voltage steps of the digitally filtered input waveform.

Abstract: A hash table controller may include a hash calculator configured to receive a key and to determine, based thereon, a first entry in a first bank of a hash table for a value associated with the key and determine a second entry in a second bank of the hash table for the value. The hash table controller also may include a table operations manager configured to determine that the first entry and the second entry are empty, and to store the value and a duplicate of the value at both the first entry and the second entry, respectively.

Abstract: According to one exemplary embodiment, a method for producing an up-converted and amplified transmission signal comprises performing a logarithmic transformation of an input transmission signal to form a logarithmically transformed transmission signal, adding the logarithmically transformed transmission signal to a logarithmic local oscillator signal to form a sum signal, and performing an antilogarithmic transformation of the sum signal to produce the up-converted and amplified transmission signal. In one embodiment, a log-antilog circuit for producing an up-converted and an amplified transmission signal comprises a transmission log block configured to receive an input transmission signal and to provide a logarithmically transformed transmission signal as a transmission log block output, and an antilog block coupled to the transmission log block. The antilog block is configured to receive a sum signal of the transmission log block output and a logarithmic local oscillator signal.

Abstract: Provided are systems and methods for providing reduced audio latency in wireless communications. One electronic system providing reduced audio latency includes a host unit for converting audio data, a digital interface coupling the host unit and a wireless transceiver, where the wireless transceiver has a controller including a rate adapter, and where the controller is configured to monitor a rate mismatch between the host unit and the wireless transceiver and to compensate for the rate mismatch using the rate adapter, thereby reducing the audio latency. One controller includes an audio codec for encoding and decoding the audio data, where the controller is further configured to align a frame of encoded audio data and a transmission packet of the wireless transceiver, thereby further reducing the audio latency.

Abstract: An apparatus is disclosed to compensate for non-linear effects resulting from the transmitter, the receiver, and/or the communication channel in a communication system. A receiver of the communication system contains an image cancellation module that compensates for images generated during the modulation and/or demodulation process. The image cancellation module includes a fine carrier correction loop to correct for frequency offsets between the transmitter and receiver. The image cancellation module includes a coarse acquisition mode and a decision directed mode. The decision directed mode allows for a larger signal-to-noise ratio for the receiver when compared against the coarse acquisition mode.

Abstract: A system and method for loop timing update of energy efficient physical layer devices using subset communication techniques. During a quiet period during which a subset of communication channels are transitioned from an active mode to a low-power mode, circuitry in the active channel can be designed to track, on behalf of the inactive channels, the phase drift due to the frequency offset. This tracking of the frequency estimation error would reduce the time required to perform a timing update for the communication channels when transitioning back to the active mode.

Abstract: Beamforming feedback frame formats within multiple user, multiple access, and/or MIMO wireless communications. A transmitting wireless communication device (TX) transmits a sounding frame to one or more receiving wireless communication devices (RXs) using one or more antennae and one or more clusters. Any antenna/cluster combination may be employed in communications between TXs and RXs. The one or more RXs receive/process the sounding frame to determine a type of beamforming feedback frame to be provided to the TX. Any one of a variety of beamforming feedback frame types and a types of information may be contained within a respective beamforming feedback frame including various characteristics of the respective communication channel between the TX and each of the various RXs. A common beamforming feedback frame format may be supported and employed by all such wireless communication devices (e.g., TX and RXs) when performing MU-MIMO operation such as in accordance with IEEE 802.11ac/VHT.

Abstract: A system and method for frequency division multiplexed high speed physical layer devices. A next generation Ethernet device can be generated through reuse of existing architectures. Multiple instantiations of an existing architecture can be supported on a given wire pair by frequency division multiplexing on a number of carriers. The multiple instantiations can enable multiple modes that can support different configurations, variable rates, and energy efficient Ethernet.

Abstract: According to one disclosed embodiment, a method for fabricating an integrated resistor in a semiconductor die includes forming a high-k dielectric over a substrate and a metal layer over the high-k dielectric, where the metal layer forms a resistive element of the integrated resistor. The method further includes forming an un-doped polysilicon layer over the metal layer, where a portion of the un-doped polysilicon layer can be selectively doped and used to form a conductive path to the resistive element of the integrated resistor. In one embodiment, the metal layer comprises a gate metal. In one embodiment, the integrated resistor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps. One disclosed embodiment is an integrated resistor formed according to the disclosed method.