Abstract: Embodiments of an RF front-end are presented herein. In an embodiment, the RF front end comprises a power amplifier (PA), a noise-matched low-noise amplifier (LNA), a balance network, and a four-port isolation module. A first port of the isolation module is coupled to an antenna. The second port of the isolation module is coupled to the balancing network. The third port is coupled an output of the PA. The fourth port is coupled to a differential input of the noise-matched LNA. The isolation module effectively isolates the third port from the fourth port to prevent strong outbound signals received at the third port from saturating the LNA coupled to the fourth port. Isolation is achieved via electrical balance. In an embodiment, the signal path coupling the antenna at the first port to the differential input of the LNA at the fourth port is shorter than a wavelength of the inbound signal received by the antenna.

Abstract: A processing system includes a plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via a 60 GHz communications. The RF data bus receives first data from at least one of the plurality of first circuit modules, and transmits the first data via 60 GHz communications to at least one of the plurality of second circuit modules.

Abstract: A data communication network for providing dynamic routing through both wireless and wired subnetworks to support wireless communication devices and wired remote stations is disclosed. In the wireless network, the wireless communication devices can be mobile RF terminals, while the wired remote stations might be personal computers attached to a wired subnet, such as an ethernet coaxial cable. The wireless network architecture utilizes a spanning tree configuration which provides for transparent bridging between wired subnets and the wireless subnets. The spanning tree configuration provides dynamic routing to and from wireless communication devices and remote stations attached to standard IEEE 802 LANs.

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract: A method and apparatus are provided for enabling a transmitter to have a substantially linear magnitude response and a substantially linear phase response. The transmitter includes first and second power amplifier drivers (PADs) having respective first and second non-linear phase responses. The first non-linear phase response is based on a first bias applied to the first PAD, and the second non-linear phase response is based on a second bias applied to the second PAD. The first and second PADs are coupled in parallel to provide a combined substantially linear phase response. According to an embodiment, the first and second PADs have respective first and second average input capacitances. Signal swings about the first and second biases vary the respective first and second average input capacitances, which may be combined to provide a combined average input capacitance that is substantially insensitive to the signal swings about the first and second biases.

Abstract: According to one exemplary embodiment, a mixer circuit comprises first and second switching branches driven by a local oscillator and an input radio frequency (RF) signal. The mixer circuit further comprises at least one capacitor coupled between the first and second switching branches for high-pass filtering of a down-converted output signal of the mixer circuit. In one embodiment, each switching branch comprises a respective mixer transistor, for example, a field effect transistor (FET). In one embodiment, the mixer circuit includes an inductor to reduce or eliminate the effects of parasitic capacitors at a resonance frequency selected to approximately match a desired RF signal frequency. In one embodiment, an inductor at resonance with parasitic capacitors produces a band pass filter for an input RF signal.

Abstract: A system and method for implementing fairness in the powering of computing devices in a power over Ethernet (PoE) application. Power supplies in a power sourcing equipment are often oversubscribed. This oversubscription can lead to starvation of certain computing devices that have power requests that are not granted relative to competing requests. A fairness consideration can be implemented to ensure that starvation conditions are avoided.

Abstract: Methods, systems, and apparatuses for ball grid array land patterns are provided. A ball grid array land pattern includes a plurality of land pads and electrically conductive traces. The plurality of land pads is arranged in an array of rows and columns. A perimeter edge of the array includes a pair of adjacent oblong shaped land pads. An electrically conductive trace is routed between the pair of adjacent oblong shaped land pads from a land pad positioned in an interior of the array to a location external to the array. The oblong shaped land pads are narrower than standard round land pads, and thus provide more clearance for the routing of traces. The oblong shaped land pads enable more land pads of the land pattern array to be routed external to the array on each routing layer, and thus can save printed circuit board component and assembly costs.

Abstract: A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes time domain training symbols and time domain data symbols. The baseband processing module includes a channel estimator operable to process the time domain training symbols to produce a time domain channel estimate, a Fast Fourier Transformer operable to convert the time domain channel estimate to the frequency domain to produce a frequency domain channel estimate, a weight calculator operable to produce frequency domain equalizer coefficients based upon the frequency domain channel estimate, an Inverse Fast Fourier Transformer operable to converting the frequency domain equalizer coefficients to the time domain to produce time domain equalizer coefficients, and an equalizer operable to equalize the time domain data symbols using the time domain equalizer coefficients.

Abstract: A method and system for allocating exchange identifications (IDs) in a fibre channel switch for fibre channel aggregation. The method included determining a number (m) of N_ports present in a back end of the switch, and distributing available exchange IDs across the number (m) of present N_ports. Each exchange ID includes (j) bits and (n) bits are used to identify each of the present backend ports, where m?2n.

Abstract: An apparatus may include a flow cache module that is arranged and configured to derive, at runtime, a custom sequence of code segments for packets belonging to a specific connection using a first packet of the specific connection and a parser module that is arranged and configured to identify packets as belonging to the specific connection using an Internet Protocol (IP) tuple of the packets, where the flow cache module is arranged and configured to apply the custom sequence of code segments to the identified packets.

Abstract: The disclosed systems and methods relate to allocating bandwidth to a plurality of ports that access a shared resource. An exemplary system may comprise a multiplexer, a table, and a scheduling circuit. The table may define when a port has access to the shared resource. The table entries may be based on the number of ports with access to the shared resource and the required bandwidth in each of the ports. The scheduling circuit controls the multiplexer according to the table, and the ports may gain access to the shared resource one port at a time.

Abstract: Methods and systems for blocker attenuation using multiple receive antennas are disclosed. In this regard, a plurality of signals may be received via a corresponding plurality of antennas and a corresponding plurality of interference-suppressed signals may be generated. The interference-suppressed signals may be generated by adjusting a gain and phase of the plurality of received signals to generate a corresponding plurality of adjusted signals, and combining the corresponding plurality of adjusted signals, respectively, with the plurality of received. The gain of the received signals may be adjusted based on a wide bandwidth signal strength measurement and a narrow bandwidth signal strength measurement. A center frequency of one or more of the plurality of antennas may be adjusted based on received signals strength measurements. A gain and/or phase adjustment of each one of said received signals may be independent of gain and/or phase adjustments of other ones of the receive signals.

Abstract: Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Abstract: A switch regulator module includes a switch and a current sensing module. The switch has an input port and an output port. The current sensing module senses a first voltage at the input port of the switch and a second voltage at the output port of the switch. The current sensing module generates a sense signal that is proportional to a current that flows through the switch based on the first and second voltages.

Abstract: Fast block acknowledgment generation is provided, via a receiving station, for a plurality of received frames to accommodate latency-sensitive data applications. The fast block acknowledgment generation includes receiving a frame of the plurality of received frames including a transmitter address, a quality of service (QoS) value, and a sequence number. A match to the transmitter address and the QoS value is conducted under a concurrent search to expedite access to a block acknowledgement (ACK) structure, the match provides an index to the block ACK structure. When a block ACK agreement exists that corresponds to the transmitter address and the QoS value, the block ACK structure is accessed based upon the index and storing an acknowledgement state for the received frame in a bitmap of the block ACK structure, and when receipt of the plurality of frames is complete, generating, queuing, and transmitting of a block ACK frame based upon the ACK policy field of the received frame.

Abstract: A system and method for multiple power over Ethernet (PoE) power supply management. Power supply status signals indicative of an operating condition of a plurality of PoE power supplies are provided to a plurality of power sourcing equipment (PSE) controller chips. Pre-configured combination logic within each of the PSE controller chips converts an indicated operational state of the plurality of PoE power supplies into a powering decision for each of the Ethernet ports served by the PSE controller chip within one microsecond.

Abstract: A settop box for streaming a television program to a network device through a network includes a central processing unit, a network interface device, a direct memory access engine, a buffer, and a memory for storing computer-executable instructions. The stored instructions cause the direct memory access engine to route time-ordered digital media data packets encoding the television program into the buffer, cause the central processing unit to add a network header to the digital media data packets, and cause the network interface device to relay the digital media data packets to a network device through the network, wherein the packets are relayed substantially without latency and with a time-ordering based on the same time-ordering of the packets in the buffer.

Abstract: RF communications received by a wireless terminal from a servicing base station are used to determine the downlink quality report and implement link adaptation decisions. This involves first implementing an initial transmission scheme between the servicing base station and the wireless terminal. Next, a current downlink quality report corresponding to the initial transmission scheme is generated by the wireless terminal and received at the servicing base station. This downlink quality report is based in whole or in part on a bit-error probability (BEP). The current downlink quality report that corresponds to the initial transmission scheme is then compared to link adaptation thresholds.

Abstract: Aspects of a method and system for utilizing a frequency modulation (FM) antenna for near field communication (NFC) and radio frequency identification (RFID) are presented. Aspects of a system for utilizing an FM antenna for NFC and RFID may include a tuning control block that enables configuration of at least one capacitor array to control a frequency for reception of signals. A processor may enable configuration of an antenna for the reception of signals wherein the frequency for the received signals is utilized for FM signal reception, and at least one of: NFC signal reception, and RFID signal reception.