Abstract: A transceiver is described that includes a power amplifier (PA), a low noise amplifier (LNA), and an impedance matching circuit having a first and second differential output node. The first and second differential output nodes are coupled to outputs of the PA and to inputs of the LNA. The impedance matching circuit provides a load impedance to the outputs of the PA. The transceiver further includes a first impedance device having an output impedance coupled between the first and second differential output nodes. In this way, the combination of the output impedance and the load impedance matches with an impedance at the inputs of the LNA.

Abstract: An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

Abstract: A radio frequency (RF) transceiver includes an RF transmitter that generates an outbound RF signal at a carrier frequency that is based on a transmitter local oscillation. An RF front-end receives an inbound RF signal that includes a desired signal component that is based on the outbound RF signal and that includes an undesired signal component. The RF front-end includes a first RF combiner module that attenuates the undesired signal component to produce a desired RF signal. A down conversion module generates a down converted signal from the desired RF signal based on a receiver local oscillation. A receiver processing module generates inbound data from the down converted signal. A frequency control module controls a frequency of the transmitter local oscillation and a frequency of the receiver local oscillation, based on an interference rejection signal, to control the attenuation of the undesired signal component.

Abstract: The present invention relates to battery chargers. A first controller can be configured to set, when a first power supply is coupled to a first port, a current produced by a variable current source at a safe rate to charge a battery. An ammeter can be configured to measure, when the battery is coupled to a second port, the current flowing into the battery. The first controller can be configured to increase, after a passing of a quantifiable amount of time, the current produced by the variable current source by a quantifiable amount of current. The first controller can be configured to continue iteratively to increase, after the passing of the quantifiable amount of time, the current produced by the variable current source by the quantifiable amount of current until the safe rate is near or at a highest safe rate to charge the battery.

Abstract: A plurality of base station devices are linked together and synchronized to facilitate communication between the respective base station devices and respective downlink subscriber stations. According to one embodiment of the invention, one of the base station devices is designated as a master device, and the other base station devices are designated as slave devices. The respective base station devices are connected to each other by means of a synchronization bus. The master base station device then generates and broadcasts a future time stamp value, which is received by the respective slave base station devices. When the time stamp counter in the master base station device reaches the transmitted value, a control signal is broadcast over the synchronization bus. The slave base station devices then retrieve the time stamp value and reset their respective local time stamp counters to the received value. In this manner, the base station devices are synchronized.

Abstract: A method for reducing the bandwidth required to transmit a data packet via a wireless network is provided. In an embodiment, the method includes generating a packet to be transmitted via the wireless network. Once a packet is generated, a packet a packet type of the packet to be transmitted via the wireless network is determined. Based on the packet type, a suppression rule is selectively applied to the packet to generate a suppressed packet. Applying the suppression rule includes suppressing at least a portion of the header of the packet and adding a descriptor associated with the header suppression rule to the packet. The method concludes with the transmittal of the suppressed packet via the wireless network.

Abstract: Memory structure, and packet-based switch including the memory structure, having Address Resolution Table and Packet Data Buffer table employing a shared memory. Transmit Descriptor Table also may share memory. Address Resolution Table can be implemented with direct mapping, for which destination address key direct-mapped address search may be used. The memory structure and switch implement an IEEE Std. 802.3 communication protocol via multiple ports.

Abstract: A RF integrated circuit (IC) includes first and second RF transceivers. A processing module generates a first and second control signals to select either a receive mode or a transmit mode for both RF transceiver, each control signal having a first value when the receive mode is selected and a second value when the transmit mode is selected. First and second transmit/receive switches, each include an on-chip microelectromechanical switch, and each respond to their corresponding control signal to implement either the transmit mode or the receiver mode.

Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

Abstract: A communication device includes a voice data and RF integrated circuit (IC) that includes a memory module that stores a least one application as a plurality of operational instructions, the at least one application having a plurality of power modes that each correspond to one of a plurality of use characteristics. A processing module executes the plurality of operational instructions and determines a selected one of the plurality of power modes based on current use characteristics of the at least one application, and the generates a power mode signal based on the selected one of the plurality of power modes. An off-chip power management circuit receives the power mode signal and that generates a plurality of power supply signals to the voice data and RF IC based on the power mode signal.

Abstract: Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation. A novel means is presented herein by which error magnitudes (or error values) can be calculated directly without requiring the generation of an error value polynomial (EVP). Modification of the Koetter decoding approach and the Forney formula are employed herein to perform the direct calculation of the error values. This approach is operable to save computation clock cycles that would normally be used to compute the EVP, and these clock cycles may be used to reduce the otherwise required parallelism and complexity in the ECC design that may be needed to perform the error correction in the allotted time and may also result in power savings. Some advantages related to this may approach include lower risk, less design time, and more scalability in an overall design.

Abstract: Herein described are at least a system and a method of reducing or decreasing the rate of interrupts transmitted by a device to a microprocessor. In a representative embodiment, the device comprises a universal asynchronous receiver/transmitter. In a representative embodiment, the rate of interrupts is reduced by receiving and using a first signal as an input to a first counter. The first counter outputs a first count, and compares the first count to a value provided by a memory. Subsequently, a second signal is generated to initiate an interrupt when the first count equals the value. In a representative embodiment, a system for delaying transmission of an interrupt from a universal asynchronous receiver/transmitter (UART) to a microprocessor comprises a counter capable of generating a count, a memory capable of storing a value, and a comparator used for comparing the count to the value.

Abstract: A radio transceiver device includes circuitry for radiating electromagnetic signals at a very high radio frequency both through space, as well as through wave guides that are formed within a substrate material. In one embodiment, the substrate comprises a dielectric substrate formed within a board, for example, a printed circuit board. In another embodiment of the invention, the wave guide is formed within a die of an integrated circuit radio transceiver. A plurality of transceivers with different functionality is defined. Substrate transceivers are operable to transmit through the wave guides, while local transceivers are operable to produce very short range wireless transmissions through space. A third and final transceiver is a typical wireless transceiver for communication with remote (non-local to the device) transceivers.

Abstract: A radio receiver front-end includes first and second RF receiver sections and an RF combining module. The first RF receiver section is coupled to receive an inbound RF signal and provide to a first representation of the inbound RF signal, wherein the inbound RF signal includes a desired signal component and an undesired signal component. The second RF receiver section is coupled to receive the inbound RF signal and to provide a second representation of the inbound RF signal. The RF combining module is coupled to combine the first and second representations of the inbound RF signal to produce a desired RF signal, wherein the desired RF signal includes the desired signal component and an attenuated representation of the undesired signal component.

Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

Abstract: An adjustable antenna interface includes a single-ended to differential conversion circuit, an adjustable impedance matching circuit, an RF differential switch, and an input. The single-ended to differential conversion circuit converts inbound RF signals from single-ended signals to differential signals and converts outbound RF signals from differential signals to single-ended signals. The adjustable impedance matching circuit provides an impedance based on an impedance control signal. The RF differential switch provides the differential outbound RF signals from the IC to the single-ended to differential conversion circuit in accordance with a first antenna control signal and provides the differential inbound RF signals from the single-ended to differential conversion circuit to the IC in accordance with a second antenna control signal. The input receives the first antenna control signal, the second antenna control signal, and the impedance control signal from the IC.

Abstract: Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

Abstract: A method and related computer program product for combining resources of multiple RAID controllers and managing them as a single entity, comprising searching the RAID controllers for the most appropriate version of the firmware to be executed, determining whether a more appropriate version of the firmware was previously loaded into system memory, unloading inappropriate versions of the firmware, loading the most appropriate version of the firmware and initializing all RAID controllers as a commonly managed entity having combined resources.

Abstract: Methods and apparatus for performing parity and/or ECC operations are disclosed. An example method includes determining that an opcode is being transmitted on a bus and determining if the transmitted opcode is a memory operation. In the event the transmitted opcode is a memory write operation, the example method includes calculating a parity bit for data associated with the opcode, writing the calculated parity bit to a parity table and writing the data to a memory. The example method also includes, in the event the transmitted opcode is the memory read operation, recovering data from a previously written memory, calculating a parity bit for the recovered data, recovering a previously stored parity bit for the recovered data, comparing the parity bit for the recovered data with the previously stored parity bit and, in the event the recovered data parity bit does not match the previously stored parity bit, providing an error notification.

Abstract: A preamble of a frame for a multiple input multiple output (MIMO) wireless communication for a first transmit antenna of the MIMO communication includes a legacy preamble portion in accordance with a legacy wireless communication protocol. The preamble of the frame for the MIMO wireless communication for the first transmit antenna also includes a current protocol preamble portion in accordance with a protocol of the MIMO wireless communication. The preamble of a frame for at least a second antenna of the MIMO communication includes a cyclically shifted legacy preamble portion for the frame. The preamble of the frame for the MIMO wireless communication for the second transmit antenna also includes a second current protocol preamble portion in accordance with a protocol of the MIMO wireless communication.