Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Abstract: Determining video content type of a video displayed on a LCD and triggering adjustment in drive power of the LCD based on the video content type. The video content type indicates relative content motion of the video. A video content type detection module is one or combination of a software and a hardware and directs the LCD to be driven relative slower or faster based upon video content. The module independently or in conjunction with another module identifies an active window from a plurality of windows corresponding to a plurality of applications running on the host device and sets the drive power of the LCD based on speed of a video displayed on the active window. The module may also adapt LCD drive power based upon user input and/or remaining battery life.

Abstract: Determining pixel behavior type of a pixel or a group of pixels of a LCD and triggering adjustment in drive power of the pixel or the group of pixels based on the pixel behavior type. The pixel behavior type indicates relative motion of areas on the LCD in a video. A pixel behavior determination module is one or combination of a software and a hardware and directs one or more selected pixels of the LCD to be driven relative slower or faster based upon content of video that the selected pixels display. The module independently or in conjunction with another module identifies an active window from a plurality of windows corresponding to a plurality of applications running on the host device and sets the drive power of those pixels that correspond to the active window based on speed of a video displayed on the active window. The module may also adapt LCD drive power on a pixel by pixel basis based upon user input and/or remaining battery life.

Abstract: A satellite communication system includes a satellite earth station operably coupled to a data network, and a plurality of satellite modems, each satellite modem of the plurality of satellite modems communicating in an upstream and downstream data communication mode with the satellite earth station via at least one servicing satellite.

Abstract: Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system.

Abstract: A system and method for enabling power applications over a single conductor pair. In one embodiment, data transformers are coupled to a single conductor pair using one or more direct current (DC) blocking elements that preserve an alternating current path. Power is injected onto the single conductor pair after the DC blocking elements and power is extracted from the single conductor pair before the DC blocking elements. Saturation of the data transformers by the injection of power onto the single pair is thereby prevented.

Abstract: Described herein is a video encoder that includes a memory unit, a selector, and an encoding processor. The memory unit stores a plurality of pictures. The selector accesses the plurality of pictures in the memory unit. The selector initially accesses a first picture, followed by another picture, followed by one or more pictures. The one or more pictures are presented to the video encoder between the first picture and the another picture. The encoding processor encodes the first picture independently, then encodes the another picture independently, and finally, the one or more pictures are encoded. The output of the encoding processor is a first coded picture, another coded picture, and one or more coded pictures respectively.

Abstract: A distributed Cable Modem Termination System (CMTS) includes a head end, a downstream transmitter hub, and a plurality of cable modems that all establish frequency lock with a common frequency reference. The head end transmits a plurality of time stamps from the head end to the plurality of cable modems via a packet data network, the downstream transmitter hub, and cable modem network plant. Each of the plurality of cable modems performs smoothing operations on the plurality of time stamps to establish phase lock with the head end. The downstream transmitter and the plurality of cable modems perform ranging operations to establish phase lock among the plurality of cable modems. In an alternate operation, the frequency reference includes marker sequences that the devices of the distributed CMTS use to establish phase lock.

Abstract: Aspects of a method and system for a high-precision frequency generator using a direct digital frequency synthesizer for transmitters and receivers may include generating a second signal from a first signal by frequency translating an inphase component of the first signal utilizing a high-precision oscillating signal that may be generated using at least a direct digital frequency synthesizer (DDFS) and at least a Phase-Locked Loop (PLL). A corresponding quadrature component of the first signal may be frequency translated utilizing a phase-shifted version of the high-precision oscillating signal. The inphase component of the first signal may be multiplied with the high-precision oscillating signal and the quadrature component of the first signal may be multiplied with the phase-shifted version of the high-precision oscillating signal. The second signal may be generated from the first signal by adding the frequency translated inphase component to the frequency translated quadrature component.

Abstract: A method and apparatus are disclosed for facilitating efficient operation of trick modes in a personal video recording (PVR) system. Stream-navigation data from a data stream is captured and pre-processed to generate a frame-correlated NAV table comprising one entry for each frame within the data stream, during recording of the data stream. The stream-navigation data comprises start code data, content rating data, and conditional access data that is embedded in the data stream. During playback of the data stream in a user-selected trick mode, the frame-correlated NAV table is used to generate command packets that are sent to a data decoder along with selected frames of the data stream. The selected frames are decoded based on information in the command packets and certain selected frames may be displayed as part of the trick mode.

Abstract: Magnetic reference patterns may be generated on a disk or other magnetic media without the need for seed wedges. This involves writing a first magnetic reference pattern to the disk with a servo writer. The disk may then be transferred to a hard disk drive. Control circuitry within the hard disk drive may recognize the first magnetic reference pattern and then position a RW head within the hard disk drive based on the first magnetic reference pattern. As the RW drive is accurately positioned based on the first magnetic reference pattern a second magnetic reference pattern may be written to the disk using the RW head. The RW head location is determined based on the velocity and phase between the read-write head and spiral sync marks contained within the first magnetic reference pattern.

Abstract: A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal.

Abstract: A system and method for managing messaging in a mobile communication system (e.g., having power-save capability) in a multiple network environment. For example, the mobile communication system may operate in a power-save mode (e.g., a mode in which the mobile communication system does not communicate messages). The mobile communication system may exit the power-save mode. After exiting from the power-save mode, the mobile communication system may determine to establish communication with a second system (e.g., a message server) over a second communication path instead of a first communication path. Communication with the second system may be established over the second communication path, and message-related information may be communicated between the mobile communication system and the second system. Such message-related information may, for example, comprise message information, information regarding message availability, or information regarding the communication of message information.

Abstract: A channel dispersion estimation algorithm(s) may be implemented within a channel length estimation module of a multi-branch equalizer processing module that disables a branch of the multi-branch equalizer processing module when the channel length or channel delay spread associated with received radio frequency (RF) bursts exceeds a predetermined threshold. The channel dispersion estimation algorithm identifies when the radio frequency (RF) bursts have a channel length or channel delay spread that can affect receiver performance. The channel length estimation module may disable interference cancellation by a branch of the multi-branch equalizer processing module in response to such a channel length or channel delay spread.

Abstract: An circuit includes a first wireless interface circuit that transceives packetized data between a host module and a first external device in accordance with a first wireless communication protocol. A second wireless interface circuit transceives packetized data between the host module and a second external device in accordance with a second wireless communication protocol. The second wireless interface circuit includes at least one module that is shared with first wireless interface circuit, the module having a first state where the module is operational and a second state corresponding to a low-power state. The first wireless interface circuit and the second wireless interface circuit operate in accordance with a wireless interface schedule that includes a first time interval where the first wireless interface device and the second wireless interface device contemporaneously use the at least one module in the first state and a second time interval where the at least one module is in the second state.

Abstract: A system (5) processes pixel data representing one of a first image compressed according to a first compression algorithm and a second image compressed according to a second compression algorithm. A pixel analyzer (32) generates first and second selection signals depending on the type of image. A processing module (40) includes first circuits arranged to process the data in response to a first selection signal and second circuits arranged to process the data in response to a second selection signal. A control processor (10) enables the first circuits in response to the first selection signal and enables the second circuits in response to the second selection signal.

Abstract: Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

Abstract: Improved apparatus for a radio communication system having a multiplicity of mobile transceiver units selectively in communication with a plurality of base transceiver units which, in turn, communicate with one or more host computers for storage and manipulation of data collected by bar code scanners or other collection means associated with the mobile transceiver units. A network controller and an adapter which has a simulcast and sequential mode provide selective interface between host computers and base transceivers. A scheme for routing data through the communication system is also disclosed wherein the intermediate base stations are organized into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically.

Abstract: An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.

Abstract: Presented herein are system(s) and method(s) for handling audio jitters. In one embodiment; there is presented a method for decoding an audio signal. The method comprises receiving a portion of the audio signal, the portions of the audio signal associated with a time stamp; comparing the time stamp associated with the portion of the audio signals to a reference time; generating another portion of the audio signal, if the time stamp is later than the time reference by over a certain margin or error; and dewindowing the another portion with a previously played portion of the audio signal, thereby resulting in a an another dewindowed portion.