Abstract: A voltage supply interface provides both coarse and fine current control with reduced series resistance. The voltage supply interface has a segmented switch having N component switches that are digitally controlled. The voltage supply interface replaces a conventional sense resistor with a calibration circuit that has a replica switch that is a replica of the N component switches. The calibration circuit includes a reference current IREF that is sourced through the replica switch. A voltage comparator forces a common voltage drop across the replica switch and the n-of-N activated component switches so that the cumulative current draw through the segmented switch is n·IREF. The current control of the voltage interface can be coarsely tuned by activating or deactivating component switches, and can be finely tuned by adjusting the reference current. The current sense resistor is eliminated so that the overall series resistance is lower.

Abstract: Transmitter calibration of a wireless device is initiated based upon an operational value of the wireless device. The calibration operations are performed over a plurality of calibration time periods, each calibration time period divided into a plurality of first interval portions interspersed with a plurality of second interval portions, for each calibration time period of the plurality of calibration time periods, respective calibration settings are applied. During the first interval portions substantially fixed first current input is applied to at least one gain adjustable element of the RF circuitry. During the second interval portions, varying current input is applied to the at least one gain adjustable element of the RF circuitry. Output levels of the RF circuitry are measured over the calibration time period. Operational calibration settings for the baseband processing circuitry and analog signal path components of the transmitter are selected based upon the calibration operations.

Abstract: A process of controlling a flow of data in a wireless network providing wireless access to the wireless network by wireless devices is disclosed. Data is received from a wireless device by a network device, through one access point of a plurality of access points in communication with the network device, indicating a client identifier for the wireless device. The client identifier is forwarded to an authentication server and the network device mediated authentication of the wireless device with the authentication server. Thereafter, data packets received from portions of the wireless network and from the plurality of access points are evaluated and the received data packets are passed to portions of the wireless network and to the plurality of access points, based on the evaluation of the received data packets. In addition, the network device periodically polls for a status of the wireless device from the access point.

Abstract: A wireless transceiver includes at least one phased array antenna, that transmits an outbound RF signal containing outbound data to at least one remote transceiver and that receives an inbound RF signal containing inbound data from the at least one remote RF transceiver, wherein the at least one phased array antenna is configurable based on a control signal. An antenna configuration controller generates the control signal to configure the phased array antenna to hop among a plurality of radiation patterns based on a hopping sequence. At least one RF transceiver section generates the outbound RF signal based on the outbound data and that generates the inbound data based on the inbound RF signal.

Abstract: An integrated circuit comprising multiple independent power supply zones at substantially the same voltage level and a method for utilizing such power supply zones. An integrated circuit may comprise a first module and may, for example, comprise a second module. A first power supply bus may communicate first electrical power to the first module, where the first electrical power is characterized by a first set of power characteristics comprising a first voltage level. A second power supply bus may communicate second power to the second module, where the second power is characterized by a second set of power characteristics comprising a second voltage level that is substantially similar to the first voltage level. The second set of power characteristics may, for example, be substantially different than the first set of power characteristics. The second power supply bus may also, for example, communicate the second electrical power to the first module.

Abstract: A composite differential Radio Frequency (RF) power amplifier includes a plurality of differential RF cascode power amplifiers coupled in parallel. Each differential RF cascode power amplifier includes a positive transconductance stage and a positive cascode stage coupled in series with the positive transconductance stage between a voltage node and ground. Each also includes a negative transconductance stage and a negative cascode stage coupled in series with the negative transconductance stage between the voltage node and ground.

Abstract: Aspects of a method and system for an efficient channel quantization method or MIMO pre-coding systems may include quantizing channel state information in a MIMO pre-coding system onto a codebook, which comprises one or more unitary matrices, using a cost function; selecting a quantization function that enables the quantizing based on a number of receive antennas and a number of transmit antennas associated with the MIMO pre-coding system; and selecting the cost function from a set of cost functions based on the number of receive antennas and the number of transmit antennas. The channel state information may be a matrix ?.

Abstract: A number of features for enhancing the performance of a communication system, in which data is transmitted between a base station and a plurality of subscriber stations located different distances from the base station, are presented. The power transmission level, slot timing, and equalization of the subscriber stations are set by a ranging process. Data is transmitted by the subscriber stations in fragmented form. Various measures are taken to make transmission from the subscriber stations robust. The uplink data transmission is controlled to permit multiple access from the subscriber stations.

Abstract: In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.

Abstract: Methods and apparatus for data communication are disclosed. An example method includes encoding a first plurality of transmitting frames, where a header segment of each frame is encoded in accordance with a fixed set of header encoding parameters and a payload segment of each frame is encoded in accordance with a first set of a variable set of payload encoding parameters. The example method also includes transmitting the first plurality of transmitting frames to a receiving station and receiving a request from the receiving station to change the first set of payload encoding parameters to a second set of the variable set of payload encoding parameters.

Abstract: Described herein is a method and system for rate estimation in a video encoder. The method and system use estimation metrics that can also be part of motion estimation and spatial prediction. A rate controller may utilize the system for rate estimation in two ways. The rate controller may supply a quantization parameter and receive a bit estimate from the rate estimator. Alternatively, the rate controller may supply a bit estimate and receive a quantization parameter from the rate estimator.

Abstract: A system and method for storing a multidimensional array of data, such as a two dimensional (2-D) array of video data, in a non-contiguous memory space. The system and method maps individually indexed elements of a multidimensional array of data from a source device into blocks of non-contiguous memory available in a destination memory system, even when the destination blocks are small and/or their size does not correlate in any way to the dimensions of a source buffer. In particular, the blocks of non-contiguous memory may be as small as a single element of the data indexed in the 2-D array.

Abstract: A composite differential Radio Frequency (RF) power amplifier includes a plurality of differential RF cascode power amplifiers coupled in parallel. Each differential RF cascode power amplifier includes a positive transconductance stage and a positive cascode stage coupled in series with the positive transconductance stage between a voltage node and ground. Each also includes a negative transconductance stage and a negative cascode stage coupled in series with the negative transconductance stage between the voltage node and ground.

Abstract: Methods and systems are disclosed for generating random numbers and initial vectors. A random number generator generates one or more random numbers that are used to repetitively seed pseudo random number generators so that the pseudo random number generators generate random numbers. Thus, a single random number generator may be used to simultaneously generate several random numbers. The random numbers generated by the pseudo random number generators may be used as initial vectors in encryption engines.

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can includeselectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract: A receiver operatively coupled to an antenna structure capable of receiving a first plurality of RF signals is disclosed herein. The receiver includes an RF processing network operative to perform weighting and combining operations within the RF domain using the first plurality of RF signals so as to produce a second plurality of RF signals. Also provided is a downconverter configured to downconvert the second plurality of RF signals into a second plurality of down-converted signals. In alternate implementations certain of the weighting and combining operations are performed at baseband and the remainder effected within the RF domain. A transmitter of corresponding architecture is also disclosed.

Abstract: A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operational circuit having at least one controllable circuit parameter. Each integrated circuit chip also includes a process monitor module at least partially constructed thereon. The controller is coupled to each process monitor module and to each operational circuit. The controller includes logic for evaluating the performance of an operational circuit based on data obtained from process monitor module and operational circuit related data stored in a memory. Based on the evaluation, the controller determines whether any deviations from desired or optimal performance of the circuit exist. If deviations exist, the controller generates a control signal to initiate adjustments to the operational circuit to compensate for the deviations.

Abstract: The present invention relates generally to computer devices utilizing removable radio frequency communication devices used for transmitting and receiving information and more particularly to an improved apparatus for connecting an appropriate antenna to the radio frequency communication device using an antenna cap, and to an improved method and apparatus for connecting a communication card device such as a radio or modem to an appropriate antenna or telephone line.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: Upstream requests such a bandwidth requests, are processed by CMTS out of order on a priority basis to reduce latency in responding to the request. Specifically, a cable modem termination system (CMTS) is connected to a plurality of cable modems by a cable plant. The CMTS has a burst receiver adapted to be connected to the cable plant to process upstream data packet units and bandwidth requests transmitted by the cable modems. Each packet includes a header that uniquely distinguishes the bandwidth requests from other data types. Packet data units are arranged in a first memory queue. Bandwidth requests are arranged in a second memory queue. The headers of the packets processed by the burst receiver are inspected as they arrive at the CMTS to determine if the packets are packet data units or bandwidth requests. Packet data units are routed to the first memory queue. Bandwidth requests are routed to the second memory queue.