Abstract: An example network device includes a processor that is configured to apply specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The example network device is configured to enable selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The specific fields include a plurality of fields some of which include multiple field values and definitions. An input bit map field of one of the plurality of fields is used to provide an additional global mask that is ANDed to associated masks in selected entries in the memory device thereby enabling the memory device to output an OR of the data in the selected entries and thereby allowing multiple ports to share a rule within a memory device entry.

Abstract: A radio frequency integrated circuit (RFIC) includes a low noise amplifier that amplifies an inbound radio frequency (RF) signal to produce an amplified RF signal. A down conversion module converts the amplified RF signal to a down converted signal based on a local oscillation. An analog to digital conversion (ADC) module coupled to convert the down converted signal into a digital signal. A baseband processing module converts the digital signal into inbound data, wherein at least one function of the baseband processing module is clocked by a plurality of baseband clock signals A clock module produces the plurality of baseband clock signals, wherein the clock module detects an interference condition when frequency dependent noise components associated with at least one of the plurality of baseband clock signals are inside a frequency band associated with the inbound RF signal, and spreads the spectrum of the at least one of the plurality of baseband clock signals when the interference condition is detected.

Abstract: An analog comparator circuit with associated hysteresis logic operably disposed to provide a logic switching mechanism based upon an input voltage level includes a voltage comparator block operably disposed to receive a voltage input signal at a positive terminal of the voltage comparator block and a selected reference voltage at a negative terminal of the voltage comparator block and is operable to produce a logic output based upon a favorable comparison. The hysteresis logic block is operable to produce one of a plurality of reference voltage levels to the negative terminal of the voltage comparator block as the selected reference voltage based upon a two-level reference signal input and further based upon a detected transition in logic of an output produced by the voltage comparator block wherein the output is received by the hysteresis logic block in a feedback signal.

Abstract: Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm is used for translating a logical block address into a physical starting location such that one or more fractional sectors may be processed during a read or write operation. A second algorithm is used for temporally processing one or more portions of a track of a disk drive, wherein the one or more portions may comprise one or more defective fractional sectors, non-defective fractional sectors, frame remainders, and servo sectors. The system comprises a memory, a processor, and software resident in said memory. The process executes the software that implements the first and second algorithms.

Abstract: According to one aspect, there is provided a method for parsing RASP events in a number of packets in a PVR-enabled set-top system using a software RASP parser. The method includes retrieving a first SCID from a first packet, determining if the first SCID is on a SCIDList, and determining if the first packet is scrambled if the first SCID is on the SCIDList. The method further includes retrieving a second SCID from a second packet if the first SCID is not on the SCIDList. The method further includes determining if the first packet is an auxiliary packet if the first packet is not scrambled. The method further includes checking for a bundle boundary RASP event if the first packet is scrambled. The method further includes parsing the first packet for a scrambled RASP event if the first packet is scrambled.

Abstract: A voice data and RF integrated circuit (IC) includes an RF transmitter, that generates an RF signal to a power amplifier module. A memory module stores a least one application as a plurality of operational instructions, the at least one application having a plurality of modes that each correspond to one of a plurality of use characteristics. A processing module executes the plurality of operational instructions and determines a selected one of the plurality of modes based on current use characteristics of the at least one application, and generates at least one control signal based on the selected one of the plurality of modes. A bias control generator generates a bias control signal in response to the at least one control signal, to control the biasing of the power amplifier module.

Abstract: A DC compensation circuit restores the frequency spectrum of an input signal at DC (or 0 Hz) by removing or reducing DC offset, 1/f noise, or any other unwanted noise at or near 0 Hz. The DC compensation is performed using direct coupling, as opposed to AC coupling, so that no useful signal information in the active period of the input signal is lost at DC. The DC compensation circuit samples the input signal during an inactive period of the input signal. Afterwhich, the unwanted DC noise is determined from the sampled signal and stored until an active period of the input signal. For example, the sampled signal can be filtered using a passband around DC so as to isolate the signal energy at DC during the inactive period. Since there is no useful signal information present during the inactive period, any signal energy at the output of the filter is necessarily unwanted DC noise.

Abstract: A multiple band direct conversion radio frequency (RF) transceiver integrated circuit (IC) includes a multiple band direct conversion transmitter section, a multiple band direct conversion receiver section, and a local oscillation module. The multiple band direct conversion transmitter section includes a transmit baseband module and a multiple frequency band transmission module. The multiple band direct conversion receiver section includes a multiple frequency band reception module and a receiver baseband module. The local oscillation generation module is operably coupled to generate a first frequency band local oscillation when the multiple band direct conversion RF transceiver IC is in the first mode and operably coupled to generate a second frequency band local oscillation when the multiple band direct conversion RF transceiver IC is in the second mode.

Abstract: A method of handling a datagram in a network device is disclosed. The steps include receiving a datagram, with the datagram having multiple field values, at a port of a network device, parsing the received datagram to obtain the field values, applying the parsed field values to a Ternary Content Addressable Memory (TCAM), determining matches between the parsed field values and predetermined criteria in the TCAM, indexing into a policy table based on the determined matches to obtain an action entry and taking an action based on the obtained action entry.

Abstract: A technique to perform a guided partial response target search for characterizing a read channel of a disk drive. A target adaptation scheme pre-selects a plurality of targets from a pool of potential targets based on certain criteria and the selected targets are sorted in linear gradient orders. When target adaptation is being performed by comparing the equalizer output with an ideal reconstructed signal, a difference value sets a gradient vector that is used to determine which direction to move along the sorted list of targets to select the next target.

Abstract: A hybrid transmitter includes first and second up-conversion modules, a combining module, and a power amplifier circuit. The first up-conversion module is operably coupled to generate a first up-conversion signal based on a normalized in-phase (I) symbol, an in-phase local oscillation, and phase or frequency information. The second up-conversion module is operably coupled to generate a second up-conversion signal based on a normalized quadrature (Q) symbol, a quadrature local oscillation, and the phase or frequency information. The combining module is operably coupled to combine the first and second up-conversion signals to produce a radio frequency (RF) signal. The power amplifier circuit is operably coupled to adjust amplitude of the RF signal based on amplitude information to produce an amplitude and phase modulated RF signal.

Abstract: A radio frequency (RF) front-end includes a power amplifier module and a power amplifier control module. The power amplifier module is coupled to amplify an outbound RF signal in accordance with a control signal to produce an amplified outbound RF signal. The power amplifier control module is coupled to generate the control signal based on at least one of forward power of the amplified outbound RF signal and reflected power of the amplified outbound RF signal.

Abstract: Methods and systems for a synchronizable E-VSB enhanced data interleaving and data expansion are disclosed. Aspects of one method may include a packet processor that may generate valid output when a portion of the packet processor may initially contain invalid data. The packet processor may generate the valid data after detecting that storage elements within an interleaver integrated within the packet processor may be filled with valid data received from input, and that a byte output by the interleaver may be a first byte among the bytes in the interleaver that may be part of a new VBS field.

Abstract: A Radio Frequency (RF) cascode power amplifier operates with differing battery supply voltages. A transconductance stage has a transistor with an RF signal input at its gate. A cascode stage has at least one cascode transistor, the cascode stage coupled in series with the transconductance stage between a battery voltage node and ground, the cascode stage having an RF signal output at the battery voltage node and at least one bias input to the at least one cascode transistor. Cascode bias feedback circuitry applies fixed bias voltage(s) to the at least one two bias inputs for a low battery voltage and applies feedback bias voltage(s) to the at least two bias inputs for a high battery voltage, the feedback bias voltage(s) based upon a voltage of the battery voltage node. More than two differing battery supply voltages are supported.

Abstract: A RF receiver includes a low noise amplifier and blocking module, a down conversion module, and a local oscillation module. The low noise amplifier and blocking module is coupled to receive an inbound RF signal, wherein the amplified inbound RF signal includes a desired RF signal component and a blocking RF signal component; attenuate the blocking RF signal component of the amplified inbound RF signal; and pass, substantially unattenuated and amplified, the desired RF signal component of the inbound RF signal to produce a desired inbound RF signal. The down conversion module is coupled to convert desired inbound RF signal into an inbound signal based on a receive local oscillation. The local oscillation module is coupled to produce the receive local oscillation, wherein the local oscillation module includes a notch filter module coupled to attenuate signal components of the receive local oscillation at frequencies corresponding to harmonics of the blocking RF signal component.

Abstract: Methods and systems for operating a physical layer device (“PHY”) in an Ethernet network include methods and systems for detecting active link partners and for selecting a mode of operation based on detected active link partners, without user intervention. The PHY monitors fiber link media and copper link media for active link partners. The PHY selects a mode of operation according to detected active link partners. For example, a serial gigabit media independent (“SGMII”) mode of operation is selected when an active copper link partner is detected and an active fiber link partner is not detected. Similarly, a serialize/deserialize (“SerDes”) pass-through mode of operation is selected when an active fiber link partner is detected and an active copper link partner is not detected. The PHY interfaces with the active copper link partner when the SGMII mode of operation is selected. Conversely, the PHY interfaces with the active fiber link partner when the SerDes pass-through mode of operation is selected.

Abstract: The method and system for channel estimation in a single channel (SC) single-input multiple-output (SIMO) system described herein may provide a fast and cost effective approach to concurrently determine propagation channel estimates in a single-transmit (1-Tx) and multiple-receive (M-Rx) antennas wireless communication system. A single weight baseband generator may comprise a set generator, a channel estimator, and an algorithm generator. The set generator may generate orthogonal function sequences that may be applied to the M receive antennas and may be utilized by the channel estimator to generate channels estimates. The orthogonal function sequences may be transferred to the channel estimator after a delay. The algorithm generator may generate phase values based on the channels estimates that may be applied to the M receive antennas to improve the system's signal-to-noise performance.

Abstract: A wireless access point and multiple wireless terminals exchange utilization, status, mobility and reception characteristics. Each wireless terminal generates reception characteristics based on transmissions received from the wireless access point and from other devices in the network. In one operating mode, the characteristics gathered by the wireless devices are forwarded to the wireless access point, and, based on all received characteristics, the wireless access point selects its own transmission power for different types of the transmission. In another mode, all characteristics are exchanged between every wireless terminal and the access point so that each can independently or cooperatively make transmission power control decisions. In a further mode, the wireless access point adjusts protocol parameters based on an assessment of the characteristics received from the client devices.

Abstract: A system, method, and apparatus for time stamping compressed video data is disclosed. A delay parameter is generated and can be encoded with the compressed video, representing the number of picture delay between the decoded sequence and the presented sequence. The presentation time stamp is associated with each of the pictures. The presentation time stamp is a function of the delay parameter and other parameters associated with picture associated therewith.

Abstract: Certain aspects of a method and system for delay matching in a rake receiver for WCDMA closed loop modes are disclosed. Aspects of one method may include selecting a set of channel estimates from a plurality of channel estimates generated for a delay matched branch and/or a non-delay matched branch in a rake receiver. A plurality of weight factors may be generated based on the selected set of channel estimates. In the delay matched branch of the rake receiver, the application of the generated plurality of weight factors may be delayed by a particular time period. A delay associated with a control channel and/or a data channel may be compensated based on the delayed application of the generated plurality of weight factors.