Abstract: A network switch and a method thereof for network communications include a first data port interface and a second data port interface supporting a data port transmitting and receiving data at a first data rate and a second data rate, respectively. The switch has a CPU interface to communicate with a CPU and a memory management unit to communicate data from at least one of the first and second data port interfaces and a memory. The switch includes a communication channel communicating data and messaging information between the first and second data port interfaces and the memory management unit and lookup tables, including an address resolution lookup table and a VLAN table. The first or second data port interfaces determine an egress port for an incoming data packet from a search of the address resolution lookup table and the VLAN table using a VLAN ID from the incoming data packet.

Abstract: A method, apparatus, and system for automatically sharing data resources between Bluetooth devices. A Bluetooth device is paired with a “trusted” Bluetooth device. When paired devices are found, the Bluetooth device automatically allows the other device to present a virtual representation of data that is shared. The shared data can be selectively downloaded for use by the other device as long as the devices are in proximity. In an alternate embodiment, the devices may share pairing information with a network, so that the same shared resource can be made available at a large number of access points but specifically only for one paired, trusted device.

Abstract: A system and method for integrated thermal monitoring in Power over Ethernet (PoE) applications. Headroom in a particular cable installation is identified using ambient temperature measurement alone or in combination with determined cable characteristics. In calculating an amount of headroom for a particular cable installation, the current capable of being carried over the cable would not be limited by worst-case cable assumptions.

Abstract: An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit.

Abstract: A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage.

Abstract: An RF transceiver includes a low noise amplifier module, a blocking circuit, a down-conversion module, a processing module, an up-conversion module, and a power amplifier module. The low noise amplifier module amplifies inbound RF signals. The blocking circuit, when enabled, substantially attenuates a blocking signal and passes, substantially unattenuated, desired receive RF signals of the inbound RF signals. The down-conversion module converts the amplified inbound RF signals or the desired receive RF signals into inbound baseband or low IF signals. The processing module converts the inbound baseband or low IF signals into inbound data, converts outbound data into outbound baseband or low IF signals, determines a transmit power level, and determines whether to enable the blocking circuit based on the transmit power level. The up-conversion module converts the outbound baseband or low IF signals into outbound RF signals, which are amplified by the power amplifier module.

Abstract: A method of communicating data to M receiving antennas from N transmitting antennas, where M and N are integers and unequal, has the steps of sending a message to determine a number of transmit paths to be used, awaiting an acknowledgement message comprising a number of receiver paths, setting the number of transmit paths based on at least the acknowledgement message, producing data streams from outbound data based on the number of transmit paths, applying the data streams to a space/time encoder to produce encoded signals and transmitting the encoded signals from at least a portion of N transmitting antennas.

Abstract: A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication.

Abstract: According to one exemplary embodiment, a transmitter module includes a line drive including a current digital-to-analog converter, where the line driver provides an analog output waveform. The current digital-to-analog converter receives a digitally filtered input waveform including at least two voltage steps. The at least two voltage steps of the digitally filtered input waveform cause a rise time of the analog output waveform to have a reduced dependency on process, voltage, and temperature variations in the line driver, while meeting stringent rise time requirements. The digitally filtered input waveform has an initial voltage level and a final voltage level, where the final voltage level is substantially equal to a sum of the at least two voltage steps of the digitally filtered input waveform.

Abstract: The present invention describes a communications system having a first link partner and a second link partner that are connected by a communications link having at least four pairs of conductors. According to IEEE Standard 802.3 (e.g. Ethernet) for 1000Base-T, a data link is maintained (in a period absent data transmission) by sending idle signals over four pairs of conductors of the cable to maintain a logical connection. This idle signal scheme is replaced with an alternate idle signaling scheme that uses only two pairs of conductors to maintain a logical connection and therefore can operate with using lower power. The other two pairs of conductors of the four pairs of conductors are unused to maintain a logical connection absent data transfer, and therefore can be used to implement a Suspend Mode of operation. During Suspend Mode, the physical layer of each link partner powers down unnecessary circuitry so as to operate in a low power environment.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: An integrated circuit includes an on-chip antenna interface, coupled to an off-chip antenna interface having at least one off-chip impedance matching component, that forms a programmable impedance matching network with the at least one off-chip impedance matching component. The programmable impedance matching network is programmable based on a control signal. An RF receiver, coupled to the programmable impedance matching network, that generates inbound data in response to a received signal from the programmable impedance matching network.

Abstract: A method to detect an event between a data source and a data sink using a trigger core is described herein. The method comprises monitoring control lines and an associated data stream for a programmable pattern, wherein the pattern is one or more of a condition, state or event. The method further comprises generating an indication by updating a status register, sending an interrupt or asserting a control line upon a pattern match.

Abstract: A communication system that includes a supervisory node (e.g., a headend) and one or more remote nodes (e.g., cable modems). Packets are transmitted between the supervisory node and the one or more remote nodes via RF channels. A plurality of the RF channels are bonded, such that packets may be transmitted via any one or more of the RF channels that are bonded. Bonding may include higher-layer bonding and/or lower-layer bonding. In higher-layer bonding, the communication system further includes a forwarder and a plurality of edge modulators. Each edge modulator is connected to a different RF channel or group of RF channels. The forwarder determines to which edge modulator one or more packets or flows are to be transmitted. In lower-layer bonding, a packet is split into pieces. The pieces are assigned to respective RF channels that are associated with an edge modulator for transmission to a remote node.

Abstract: An integrated circuit (IC) device package is presented. A frame body has opposing first and second surfaces and a central opening that is open at the first and second surfaces. The second frame body surface is mounted to a first stiffener surface. An IC die is mounted to the first stiffener surface within the central opening through the frame body. A planar lid has opposing first and second surfaces. The second lid surface is coupled to the first frame body surface. A first substrate surface is coupled to a second stiffener surface. An array of electrically conductive terminals is coupled to a second substrate surface. The stiffener, frame body, and lid form an enclosure structure substantially enclosing the IC die. The die enclosure spreads heat from the IC die, and shields EMI emanating from and radiating toward the IC die. At least one tab protrudes from the second surface of the frame body. At least one receptacle formed in the first surface of the stiffener corresponding to the at least one tab.

Abstract: Methods and systems for measuring and optimizing integrated antenna performance are disclosed and may include transmitting FM signals over a range of frequencies utilizing one or more antenna configurations. The FM transmitter may be calibrated based on a signal received by one of a plurality of wireless protocol receivers in the wireless device. The wireless device may include one or more other corresponding transmitters that utilize other wireless protocols. The transmitted FM signals may be received by a test set, which may then transmit a signal utilizing a different wireless protocol for adjusting the FM transmitter. The frequency of the transmitted FM signals may be varied utilizing a tunable oscillator, and the antenna configurations may be adjusted accordingly by impedance matching them to the FM transmitter. The FM transmitter and FM receiver and the tunable oscillator may be integrated within a single chip.

Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Abstract: The present invention provides a method for carrier detection associated with the receipt of MIMO RF packet communications. This involves receiving multiple MIMO RF packet communications with multiple receiver pathways, wherein the RF packet communications each comprise a preamble and data. The RF packet communications are sampled by a carrier detector before, during or after conversion to baseband. The carrier detectors are used to produce a set of carrier detection metrics for each reception pathway. These carrier detection metrics may be combined arithmetically with those of other reception pathways to produce a multi-reception pathway carrier detect. Alternatively, these carrier detection metrics can be processed to produce a logical decision or binary detection signal value associated with each reception pathway, which is then logically combined with the logical decisions of other reception pathways to produce a multi-reception pathway carrier detect.

Abstract: A multiple frequency antenna array includes a first antenna circuit and a second antenna circuit. The first antenna circuit has a first radiation pattern and is tuned to a first carrier frequency. The first antenna circuit transmits a first representation of a radio frequency (RF) signal at the first carrier frequency, where the first carrier frequency corresponds to a carrier frequency of the RF signal and a first frequency offset. The second antenna circuit has a second radiation pattern and is tuned to a second carrier frequency. The second antenna circuit transmits a second representation of the RF signal at the second carrier frequency, where the second carrier frequency corresponds to the carrier frequency of the RF signal and a second frequency offset.

Abstract: In a multimedia system, a method and system for deglitching in a mobile multimedia processor are provided. A deglitching operation may be provided to reduce noise and compensate for strobe signal delays that may result in false bus cycles and other operating errors. A circuit comprising a plurality of delay cells, a multiplexer, and a latch may be utilized to perform the deglitching operation. The delay cells may be selected from several delay options having different time delays based on operating temperature and applied supply voltage. The time delay may be programmable and may be dynamically varied in accordance with the operation of the mobile multimedia processor.