Abstract: In a video processing system, a method and system for a mobile receiver architecture for US Band cellular and VHF/UHF broadcasting are provided. Received channels may be processed in at least one radio frequency front end (RFFE) in a mobile terminal and may comprise at least one of a VHF/UHF broadcast channel and World band cellular channels capable of carrying voice and data. The cellular channels may be WCDMA 1900 or 850 MHz and GSM 1900 or 850 MHz. A single cellular/broadcast radio frequency integrated circuit (RFIC) may be utilized for processing the received channels. In another embodiment, a cellular band RFIC may process the EU band cellular channels and a broadcast RFIC may process the broadcast channel. Moreover, a first RFIC may process the WCDMA channels, a second RFIC may process the GSM channels, and a broadcast RFIC may process the broadcast channel.

Abstract: A method of managing traffic in a communications channel includes the steps of receiving a subscriber ID corresponding to a subscriber, performing a spectral analysis on a signal received from the subscriber within a time interval identified by the subscriber ID, and adjusting transmission characteristics of the subscriber based on the spectral analysis.

Abstract: A hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. Copies of data, program code and processing resources are migrated from their source toward requesting destinations based on request frequency, communication link costs and available local storage and/or processing resources. Each appropriately configured network device acts as an active participant in network migration. In addition, portable two-dimensional (2-D) code reading terminals are configured to wirelessly communicate compressed 2-D images toward stationary access servers that identify the code image through decoding and through comparison with a database of images that have previously been decoded and stored.

Abstract: Embodiments of the present invention provide systems and methods for automatic amplifier gain profile control, including a method for automatically configuring a variable gain profile amplifier according to received input and a variable gain profile amplification system. Further, embodiments of the present invention provide systems and methods for increased gain profile accuracy, including methods and systems to reduce the effects of temperature and/or process variations on the gain profile of an amplifier.

Abstract: Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A system and method for tunneling control over a MAC/PHY interface for legacy ASIC support. Energy efficient Ethernet control or status information can be communicated over a MAC/PHY interface using control codes that are embedded in sequence ordered sets. These sequence ordered sets would not affect the data flow and can be tunneled within an existing interface (e.g., XAUI, XFI, xxMII or derivative interfaces) without generating errors.

Abstract: Communication device employing LDPC (Low Density Parity Check) coding with Reed-Solomon (RS) and/or binary product coding. An LDPC code is concatenated with a RS code or a binary product code (e.g., using row and column encoding of matrix formatted bits) thereby generating coded bits for use in generating a signal that is suitable to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. and various implementations of cyclic redundancy check (CRC) may accompany the product coding and/or additional ECC/FEC employed. The redundancy of such coded signals as generated using the principles herein are in the range of approximately 20% thereby providing a significant amount of redundancy and a high coding gain. Soft decision decoding may be performed on such coded signal generated herein.

Abstract: A system and method for mirroring power over Ethernet (PoE) registers in physical layer devices (PHYs) over a single isolation boundary. PHYs in a PoE system can be arranged in a master/slave configuration. In this configuration, a master PHY can be designed to communicate with the power source equipment controllers via a single isolation device.

Abstract: Systems and methods for reducing the latency and for increasing throughput for MoCA devices that are connected via a coax network are provided. One method according to the invention includes, in a network having a plurality of network modules, each of the plurality of network modules being connected to a coax backbone, communicating over the coax backbone between the plurality of network modules. The method further includes a requesting the use of aggregated messages. The method further includes aggregations of messages at the Ethernet packet layer and/or at the MAC layer. The resulting messages can be received while making more efficient use of the MoCA network.

Abstract: A radio frequency (RF) transmitter front-end includes a digital to analog conversion module and a power amplifier module. The digital to analog conversion module is coupled to convert amplitude information into analog amplitude adjust signals when a first mode is active and is coupled to convert power level information into analog power level signals when a second mode is active. The power amplifier module is coupled to amplify first phase modulated RF signals in accordance with the analog amplitude adjust signals to produce first outbound RF signals when the first mode is active and is coupled to amplify second phase modulated RF signals in accordance with the analog power level signals to produce second outbound RF signals when the second mode is active.

Abstract: An impedance transformer includes a first winding and a second winding. The first winding includes a first plurality of winding components, wherein each of the first plurality of winding components is on a corresponding layer of a first set of layers of a supporting substrate. The second winding includes a second plurality of winding components, wherein each of the second plurality of winding components is on a corresponding layer of a second set of layers of the supporting substrate and the first and second sets of layers are interleaved. The first winding has a first impedance within a desired frequency range and the second winding has a second impedance within the desired frequency range, where the first and second impedances are based on at least one of spacing, trace width, and trace length of the first and second plurality of winding components.

Abstract: A system and method for the secure storage of executable code and the secure movement of such code from memory to a processor. The method includes the storage of an encrypted version of the code. The code is then decrypted and decompressed as necessary, before re-encryption in storage. The re-encrypted executable code is then written to external memory. As a cache line of executable code is required, a fetch is performed but intercepted. In the interception, the cache line is decrypted. The plain text cache line is then stored in an instruction cache associated with a processor.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions.

Abstract: A wireless communication device includes a host module. A first wireless interface device transmits a first outbound packet in accordance with a first wireless communication protocol at a first power level and a first rate during a first time interval and that transmits a second outbound packet at a second power level and a second rate during a second time interval, wherein the first power level is less than the second power level and wherein the second rate is less than the first rate. A second wireless interface device transceives data between the host module and a second external device during the second time interval in accordance with a second wireless communication protocol. An antenna section provides at least one radio frequency communication path between the first wireless interface device and the first external device and between the second wireless interface device and the second external device.

Abstract: An integrated circuit radio transceiver and associated method comprises a multi-mode device operable to support personal area network communications as well as traditional wireless local area network communications. In one embodiment, IEEE 802.11 protocol IBSS communications are used to transport Bluetooth communication data packets. Thus, the multi-mode device is operable to establish traditional BSS communications with an Access Point in addition to establishing peer-to-peer communications with another multi-mode device to transport the Bluetooth communications over the 802.11 IBSS communication link.

Abstract: A method and system of processing sampled voice packets from a voice packet sender for transmission over a bit-rate sampled data transmission system, such as by a cable modem over a cable modem termination system, to a voice packet recipient. Unsolicited grant arrivals in response to a request from the voice packet sender coupled to the cable modem are determined. The storing of sampled voice packets is synchronized with the unsolicited grant arrivals. Upon receipt of an unsolicited grant arrival, currently stored sampled voice packets are transmitted to the cable modem for further transmission to the voice packet recipient over the cable modem termination system.

Abstract: A network device for dynamically allocating memory locations to plurality of queues. The network device includes an assigning means for assigning a predefined amount of a temporary memory buffer and a shared memory buffer to each of a plurality of ports and for allocating a fixed allocation of the temporary memory buffer and the shared memory buffer to each of a plurality of queues associated with each port. After each queue has accumulated a predefined portion of data in the temporary memory buffer, the data is transmitted to the shared memory. The means for assigning reduces the shared memory access bandwidth by a predefined amount that is less than a processing bandwidth of a system clock.

Abstract: According to one exemplary embodiment, a termination circuit includes a number of drivers configured to receive source data on an input bus and to drive an output bus including a number of output lines. In the termination circuit the output lines are terminated by resistors, where one resistor is coupled between each output line and a common capacitor node. The termination circuit further includes a virtual regulator at the drivers, configured to control a termination voltage at the capacitor node by inputting compensation data into the drivers during idle cycles to achieve a net average 50% duty cycle. The virtual regulator can determine which cycles are idle by detecting an idle code in the source data.