Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: A network device for handling data and a method for handling data in a network device are disclosed. The network device includes at least one media port and at least one high speed docking station, communicating with the at least one media port. At least one master is provided in the network device, where the at least one master is connected to the at least one high speed docking station. The master is configured to handle and process data received by the at least one media port and passed to the master through the at least one high speed docking station. The network device is configured to handle media ports of different media types. Thus, the device can handle data received through different media ports that have different media types with the same master, making the network device easily configured to meet a customer's needs.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A system and method for encoding dynamic image information for an image generated by a computer application executing on a processor. Various aspects of the present invention may comprise determining a first set of information describing a reference image. A second set of information may be determined for describing an image, wherein the second set of information comprises information indicative of movement between the image and the reference image. For example, a set of primary movement directions may be determined based at least in part on the computer application generating the image. Such set of primary movement directions may be utilized for analyzing the image relative to the reference images. The difference between the image and the reference image may, for example, be analyzed using at least one of the set of primary movement directions. A movement direction may, for example, be utilized to describe the image.

Abstract: An ATM network traffic shaper is implemented in hardware. The traffic shaper shapes transmit data on one or more virtual circuits (VCs) according to the specified quality of service (QoS) parameters. Thus, the traffic shaper provides for the delivery of associated data cells in accordance with the specified QoS parameters. The traffic shaper is scalable in that the number of supported VCs can be increased with a relatively small increase in the size of the device and associated logic gates. The traffic shaper supports constant bit rate (CBR), variable bit rate (VBR), and unknown bit rate (UBR) service types and generates cell transmit requests with zero cell delay variation (CDVT). The traffic shaper also provides very high resolution in terms of bit rate specification. Varying shaping resolutions are achieved by varying a shaping interval time (SIT) generated by a SIT counter.

Abstract: A wireless communication system is adapted for compatible inter-operation of a plurality of devices operating in accordance with a plurality of protocols. The wireless communication system includes a first group of one or more subscriber stations that interface with a base station in accordance with a first protocol and a second group of one or more subscriber stations that interface with the base station in accordance with a second protocol. The base station includes a protocol processor that identifies transmissions from the first and second groups of subscriber stations and routes transmissions from the first group of subscriber stations to a first processor operating in accordance with the first protocol and routes transmissions from the second group of subscriber stations to a second processor operating in accordance with the second protocol.

Abstract: The variable gain amplifier includes a forward path that provides the amplifier variable gain, and a feedback path. The feedback path uses a switch that is turned on at low gain levels. The switch taps into the feedback resistor, shunting it to signal-ground and eliminating the feedback mechanism. This ensures that the input impedance seen at the input port does not grow excessively, using part of the feedback resistor as a passive termination at low gain levels. In this way variable gain ranges in excess of 30 dB can be achieved.

Abstract: Aspects of a method and system for signal generation via a PLL with undersampled feedback are provided. In this regard, the output of a VCO may clock a DDFS to generate a sampling frequency, and the output of the VCO may be undersampled at the sampling frequency to generate a feedback signal for controlling the VCO. Additionally, a control word for controlling the DDFS may be generated, and may be based on a phase difference between the feedback signal and a reference signal. The sampling frequency may be determined such that an aliasing product of the undersampling occurs at a frequency of the reference signal. Also, the feedback signal may be filtered to select a desired aliasing product from a plurality of aliasing products. The output of the VCO may be frequency divided before clocking the DDFS, and a divisor of the division may be programmatically controlled.

Abstract: A multi-mode RFID tag includes a power generating and signal detection module, a baseband processing module, a transmit section, a configurable coupling circuit, and an antenna section. In near field mode, the configurable coupling circuit is operable to couple the transmit section to a coil or inductor in the configurable coupling circuit to transmit an outbound transmit signal using electromagnetic or inductive coupling to an RFID reader. In far field mode, the configurable coupling circuit is operable to couple the transmit section to the antenna section, and the multi-mode RFID tag then utilizes a back-scattering RF technology to transmit the outbound transmit signal to RFID readers.

Abstract: Position based WPAN (Wireless Personal Area Network) management. Based on either the relative position or the specific location of devices within a WPAN, communication between the various devices is managed by grouping the devices into two or more groups. In addition, the communication between theses various devices may be governed by profiles assigned to the groups (or even the actual individual devices) that are assigned based on their locations within the WPAN. The relative locations of the devices may be made using ranging that is performed by transmitting UWB (Ultra Wide Band) pulses between the various devices within the WPAN. Alternatively, each device may include GPS (Global Positioning System) functionality and information corresponding to the specific locations of the devices may be communicated between the devices, and that information may be used to group devices user and/or assign profiles to govern the communication to and from the devices.

Abstract: Packet loss concealment systems and methods are described that may be used in conjunction with a Bluetooth® Low-Complexity Sub-band Coding (LC-SBC) codec or other sub-band codecs, including but not limited to an MPEG-1 Audio Layer 3 (MP3) codec, an Advanced Audio Coding (AAC) codec, and a Dolby AC-3 codec.

Abstract: A method for flexibly configuring default values of a network device and a network device using such flexible configuration method is described. First, it is determined whether the default values are obtained through a microprocessor interface or a memory interface. When it is determined that the default values are obtained through the memory interface, a header is received from a memory through the memory interface it is determined from the header whether any default value of the network device should be updated. If the network device should be updated, then at least one configuration instruction is fetched from the memory and the at least one configuration instruction is interpreted. A register default value of the default values is changed, corresponding to the interpreted at least one configuration instruction.

Abstract: A method of switching packets in a network switch includes the step of receiving a packet on a source port of a network switch. Thereafter, the method includes the step of determining whether the network switch has sufficient memory capacity to process the data packet; and if memory capacity is sufficient, then the method reads a selected portion of the packet to determine if the packet is to be sent to a mirrored port. If mirroring is determined, then the method sends the data packet to the mirrored port. The method also includes the step of determining whether the packet is to be sent to a remote CPU for further handling, and sending the data packet to the remote CPU if appropriate. The method additionally includes the step of determining whether the packet is a unicast packet, and if so, placing the packet on an internal communication channel within the network switch for appropriate storing and forwarding.

Abstract: A video and graphics system provides square graphics pixels to blend images having 640×480 pixels, such as graphics images provided by some set top boxes and intended to be displayed at a 12.27 MHz display sample rate, with images having 704×480 pixels, such as ITU-R 601 compliant images such as NTSC SDTV images, having oblong pixels and displayed at a 13.5 MHz display sample rate. A sample rate converter including a multi-phase-multi-tap filter is used to generate square pixels. The multi-phase-multi-tap filter provides a good balance of sharpness, smoothness, anti-aliasing and reduced ringing. The multi-phase-multi-tap filter can also be used to convert images having 320×480 pixels to images having 704×480 pixels. The multi-tap filter can be used for scan rate conversion of graphics or video images for HDTV or SDTV applications.

Abstract: A method and apparatus for tagging digital photographs with geographic location data is described. In one example, a digital camera includes an imaging unit, a radio frequency/intermediate frequency (RF/IF) front end, and a memory. The imaging unit is configured to generate digital photographs. The RF/IF front end is configured to receive satellite positioning system signals and generate digital samples therefrom. The memory is configured to store a set of digital samples generated by the RF/IF front end with each digital photograph generated by the imaging unit. The digital samples produced by the RF/IF front end may be intermediate frequency samples and may include both in-phase samples and quandrature samples. Notably, the memory stores digital samples of GPS signals, rather than location data. The digital GPS samples may be processed by an off-line processing unit, such as a computer, to produce location data.

Abstract: A method for avoiding signal interference between a first RF device and a second RF device is provided. The first and second RF devices are co-located and the first RF device is configured to operate within a semi-stationary range of a frequency band. The second RF device is configured to operate by changing channels within the frequency band. The method initiates with a communication interface being provided between the first RF device and the second RF device. Then, the second RF device receives the semi-stationary range and a mode for the first RF device through the communication interface. Next, the second RF device is adapted to avoid the semi-stationary range of the frequency band of the first RF device when the mode of the first RF device is in an active mode. An apparatus where two RF devices are co-located without causing interference for each other is also provided.

Abstract: ACS (Add Compare Select) implementation for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. During each processing iteration, an ACS module generates a hard decision for each of two trellis stages, as well as a corresponding reliability for each of the two hard decisions. Also, the ACS module is operative to generate the updated state metric for the state at the current trellis stage. Multiple operations are performed simultaneously and in parallel, and control logic circuitry and/or operations employed to select which of the multiple simultaneously-generated resultants is to be employed for each of the hard decisions, reliabilities, and next state metric for the current trellis stage.

Abstract: A flip chip package generally includes a substrate, a flip chip die, and a heat spreader. The flip chip die is coupled to the substrate. The heat spreader is coupled to the flip chip die. The heat spreader can include one or more walls. Generally, the one or more walls at least partially laterally surround the flip chip die and/or the substrate. The walls can completely laterally surround the flip chip die to define a cavity in the heat spreader. The flip chip package can further include an encapsulate. For example, the encapsulate can be injected between the one or more walls of the heat spreader and the flip chip die and/or other components of the flip chip package. The encapsulate and/or the one or more walls of the heat spreader can protect one or more components of the flip chip package against moisture, corrosives, heat, or radiation, to provide some examples.

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract: A two way communication system is adapted for compatible inter-operation of a plurality of devices operating in accordance with a plurality of protocols. The communication system includes a first group of one or more remote devices that interface with a local host in accordance with a first protocol and a second group of one or more remote devices that interface with the local host in accordance with a second protocol. The local host includes a protocol processor that identifies transmissions from the first and second groups of remote devices and routes transmissions from the first group of remote devices to a first processor operating in accordance with the first protocol and also routes transmissions from the second group of remote devices to a second processor operating in accordance with the second protocol.