Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: Methods and systems for a transmitter LOFT cancellation scheme that maintains IQ balance are disclosed. Aspects of one method may include providing current compensation to both differential inputs of a mixer for each of I and Q channels. An initial current compensation of X units may be provided, followed by subsequent compensation as needed. The initial compensation may be provided to each differential input of the mixers used for I and Q channels. The subsequent current compensation for the I channel may be independent of the subsequent current compensation for the Q channel. Subsequent current compensation to a first differential input for a mixer may be increased by Y units while decreasing current compensation to the second differential input of the mixer by Y units. In this manner, the DC common mode level for the mixer may remain the same at the initial DC compensation current of X units for both mixers.

Abstract: An integrated circuit device for use in connecting synchronous optical networks to packet networks and synchronous time division multiplexed subscriber lines and a method of operation of same is disclosed. An embodiment of the invention may include SONET/SDH compatible optical carrier framing, cross connect, and packet mapping functionality. In addition, it may support Ethernet packet network connections and DS1/E1 and DS3/E3 time division multiplexed subscriber circuits, and may include a telecom bus compatible interface for the connection of additional communications devices. An embedded microprocessor core and embedded memory may permit the present invention to support enhanced remote diagnostic, trouble reporting, traffic management, and software update capabilities.

Abstract: A radio frequency (RF) transmitter includes a modulation controller that generates a modulation control signal having either a first value or a second value. A driver generates an RF signal based on an upconverted signal, wherein the driver modulates the upconverted signal based on a first modulation signal when the modulation control signal has the first value. A power amplifier generates a transmit signal based on the RF signal, wherein the power amplifier modulates the RF signal based on a second modulation signal when the modulation control signal has the second value.

Abstract: A disclosed embodiment is a low-cost, low-power system for run time estimation of a battery utilized by an electronic device. The system comprises a voltage capture circuit configured to measure a voltage of the battery and a coulomb counting circuit configured to measure a charge of the battery. Additionally, the voltage capture circuit is configured to measure an open-circuit voltage of the battery during a sleep mode, or battery voltage during an operation mode, and the coulomb counting circuit is configured to measure a discharge of the battery during the sleep mode, or a change or discharge of battery during an operation mode. The voltage capture circuit comprises a sample-and-hold circuit and an analog-to-digital converter, while the coulomb counting circuit comprises a sigma-delta converter, a comb filter, and a digital accumulator.

Abstract: A method and apparatus for controlling data flow across a network performs a method which includes transmitting a packet request message from a first station to a second station, then determining if the packet request message is valid. A request acknowledge message is transmitted from the second station to the first station, and it is then determined if the request acknowledge message is valid. The packet request message and the request acknowledge message each includes a control bit string, an identification bit string, and at least one parity bit.

Abstract: An apparatus includes an RFID transceiver, a processing module, and a wireless communication module. The RFID transceiver receives an RFID signal from a device and obtains communication information from the RFID signal. The processing module is operable to: determine a wireless communication protocol and device identification information from the communication information; receive an outbound data request; and generate outbound data in accordance with the outbound data request, wherein the outbound data includes at least a portion of the identification information. The wireless communication module converts outbound data into an outbound wireless signal in accordance with the wireless communication protocol.

Abstract: A configurable transceiver includes an RF receiver that generates a stream of inbound data from at least one received RF signal, wherein the RF receiver is configurable in response to a control signal. An RF transmitter generates at least one RF signal from a stream of outbound data, wherein the RF transmitter section is configurable in response to the control signal. A configuration controller generates the control signal based on channel data. A power management unit generates at least one receiver supply signal and at least on transmitter supply signal in accordance with a plurality of power consumption parameters, and wherein the power management unit adjusts at least one of the plurality of power consumption parameters based on the control signal.

Abstract: A communication device includes a wireless telephony transceiver for communicating first data with a wireless telephony network. One or more interface devices generate user data based on an action of a user. A processing module generates second data, based on the user data and based on first remote control configuration data corresponding to a first external device. A millimeter wave transceiver communicates the second data with the first external device via a millimeter wave communication path.

Abstract: A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes time domain training symbols and time domain data symbols. The baseband processing module includes a channel estimator operable to process the time domain training symbols to produce a time domain channel estimate, a Fast Fourier Transformer operable to convert the time domain channel estimate to the frequency domain to produce a frequency domain channel estimate, a weight calculator operable to produce frequency domain equalizer coefficients based upon the frequency domain channel estimate, an Inverse Fast Fourier Transformer operable to converting the frequency domain equalizer coefficients to the time domain to produce time domain equalizer coefficients, and an equalizer operable to equalize the time domain data symbols using the time domain equalizer coefficients.

Abstract: A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.

Abstract: A disclosed method comprises adaptive offset values in an open-circuit voltage lookup table, a temperature lookup table, and an age lookup table, and then determining a present charge of the battery utilizing an open-circuit voltage of the battery and a temperature of the battery, determining a low-voltage-alarm charge of the battery utilizing a discharge current of the battery and an age of the battery, and utilizing the present charge and the low-voltage-alarm charge to estimate the run time of the battery. Utilizing the open-circuit voltage, temperature, and age comprises looking up a present battery capacity, temperature coefficient, and ageing coefficient in lookup tables, and adjusting the present battery capacity, temperature coefficient, and ageing coefficient by the respective offset values adaptive to the battery. Estimating the run time of the battery comprises, in one embodiment, dividing the difference of the present charge and the low-voltage-alarm charge by the discharge current.

Abstract: Data packets transmitted over a wireless network are suppressed by hardware at the transmitting end and expanded on the receiving end. This conserves bandwidth as well as reduces the processing resource requirements in both the subscriber station and the base station. An extended header element is added to a data packet that is to be transmitted over the wireless network. The extended header element contains an index that is used along with an identifier to access a rule. The rule is used to determine which bytes are to be suppressed at the transmitter and expanded at the receiver.

Abstract: De-ringing operation for image processing. A selective image processing means is presented herein by which high frequency content is preserved while also eliminating ringing within digital images, and this is achieved without introducing aliasing. Based on the analysis of neighboring pixels, one or more of multiple filter modules and/or multiple image filtering/processing means is/are selectively applied to generate an output sample for a given pixel location. Two measures (e.g., local activity (LA) and edge strength (ES)) are calculated based on processing at least two different groups of pixels near a desired output sample. One of these groups of pixels may be a subset of another of the groups of pixels. By analyzing these two measures (e.g., LA and ES), selective processing of pixels near the desired output location ensures that high frequency content within the digital image is preserved with substantially reduced and/or eliminated ringing therein.

Abstract: A communication device includes a wireless telephony transceiver for communicating first data with a wireless telephony network. A millimeter wave transceiver communicates second data with a vehicle via a millimeter wave communication path. A processing module executes a plurality of applications including a wireless telephony application that is based on the communication of the first data, and a vehicle interface application that is based on the second data.

Abstract: Probe data is directly communicating between a probe device and a component of an external device via a wireless millimeter wave communication path. A probe application is executed in accordance with the probe data, for diagnostics and testing, to update component software, and to upload other files and applications to the component.

Abstract: A transceiver includes an RF receiver section having a plurality of RF receiver stages configured in parallel, and a configurable RF transmitter section. The plurality of RF receiver stages are selectively enabled in response to a control signal. The configurable RF transmitter section is configured to operate in one of: a mixed signal mode of operation and a phase modulation mode of operation, in response to the control signal.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective.

Abstract: A universal serial bus device includes a wireless millimeter wave transceiver that communicates first data with a host device via a first RF millimeter wave communication path. A USB interface, when coupled to a host device, communicates second data with the host device.

Abstract: Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.