Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard.

Abstract: A sensor is implemented in an integrated circuit. The sensor includes one or more sensor pads that are provided at or near a surface of the integrated circuit. One or more integrated circuit components such as a sense amplifier are provided in the integrated circuit die adjacent the sensor pads. One or more other components are provided in the integrated circuit die adjacent the sensor pads.

Abstract: A wireless access point and multiple wireless terminals exchange utilization, status, mobility and reception characteristics. Each wireless terminal generates reception characteristics based on transmissions received from the wireless access point and from other devices in the network. In one operating mode, the characteristics gathered by the wireless devices are forwarded to the wireless access point, and, based on all received characteristics, the wireless access point selects a client device for the relay of communications between itself and another client device. In another mode of operation, the access point selects a relay proxy on a transmission by transmission basis. In response to a request, a servicing client device repeats intercepted transmissions sent by a client device and intended for the access point.

Abstract: A method and system for discovering interconnections between a plurality of network devices arranged in a stacked configuration is provided. A probe packet, including a tag indicating a transmit port from which the probe packet was transmitted and a receive port at which the probe packet was received, is sent from one network device to a next network device. A routing packet is sent from each of the network devices, including information regarding the configuration of the stack of network devices. A master network device is elected. The master network device sends a topology packet, which includes final configuration information, to the other network devices.

Abstract: A method of handling data packets in a network device and an apparatus for handling data packets in a network device are disclosed. The method includes receiving an incoming data packet and the incoming data packet is parsed to obtain a portion of the incoming data packet. That portion is compared with rules stored in a rule table, where each rule specifies a set of actions. A match between the portion and a particular rule of the rules is selected and a particular set of actions, specified by that particular rule is executed. Each rule includes a mask, a selection flag and a validity check that are used in the comparison of the portion with each rule. The rules may be compared with the packet portion serially or in a parallel fashion and if more than one rule matches the portion, the highest priority is selected as the matching rule.

Abstract: Certain embodiments of the invention may be found in a system and method for implementing graphics and a video scaling algorithm using interpolation based on symmetrical polyphase filtering. A video or graphics scaler may be utilized to scale luma, chroma, and/or alpha information in a video image. The scaler may comprise a first symmetric polyphase sub-filter with zero phase shift that generates an in-phase filtered pixel and a second symmetric polyphase sub-filter that generates an out-of-phase filtered pixel. The video scaler may also comprise an interpolator that may generate a scaled video image pixel based on the generated in-phase and out-of-phase filtered pixels and a scaling factor. The scaling factor may be determined based on an input video size (M) and a desired output video size (N). The interpolation of the generated in-phase and out-of-phase pixels in the video scaler may be implemented by utilizing a Farrow structure.

Abstract: An analog-to-digital converter (ADC) is provided. The ADC includes a reference voltage generator configured to generate reference voltages, an analog to digital converter core configured to receive an input signal and the reference voltages and to generate a digital signal representative of the input signal, the digital signal having a number of bits, and a controller configured to determine a quality of the input signal, and, based on a quality of the input signal, to control the number of bits of the digital signal and values of the reference voltages.

Abstract: A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.

Abstract: According to the present invention, Bluetooth master device offset information is determined and distributed among the master devices within a Bluetooth network. The system either provides an offset to each master device or determines master device offsets and distributes this information to master devices within the system to allow or efficient hand-offs of a slave between master devices.

Abstract: In the current invention, a method and apparatus for automatically managing fragmentation on a disk is described. This is done by having a special Mode for preallocation and dumping of contiguous block chunks.

Abstract: A network controller may split, via a pass-through driver, processing of transmit and/or receive network traffic handled by the network controller. Physical layer (PHY) processing and/or Medium Access Control (MAC) processing of the management traffic may be performed internally via the network controller. The pass-through driver may route at least a portion of management traffic carried via the transmit and/or receive network traffic externally to said network controller for processing. In this regard, the pass-through driver may enable routing of data and/or messages to enable performing the external processing of management traffic. An application processor may be used to perform the external processing of management traffic.

Abstract: Algebraic method to construct LDPC (Low Density Parity Check) codes with parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. A novel approach is presented by which identity sub-matrices undergo cyclic shifting, thereby generating CSI sub-matrices that are arranged forming a parity check matrix of an LDPC code. The parity check matrix of the LDPC code may correspond to a regular LDPC code, or the parity check matrix of the LDPC code may undergo further modification to transform it to that of an irregular LDPC code. The parity check matrix of the LDPC code may be partitioned into 2 sub-matrices such that one of these 2 sub-matrices is transformed to be a block dual diagonal matrix; the other of these 2 sub-matrices may be modified using a variety of means, including the density evolution approach, to ensure the desired bit and check degrees of the irregular LDPC code.

Abstract: An integrated circuit (IC) includes a baseband processing module, a GPS receiver, and an RF section. The baseband processing module is coupled to process voice signals and data signals. The global positioning satellite (GPS) receiver module is coupled to process GPS signals. The radio frequency (RF) section id coupled to: transceive the voice signals as RF voice signals; transceive the data signals as RF data signals; and convert GPS RF signals into the GPS signals.

Abstract: A method and system for handling received out-of-order network data using generic buffers for non-posting TCP applications is disclosed. When incoming out-of-order data is received and there is no application buffer posted, a TCP data placement may notify a TCP reassembler to terminate a current generic buffer, allocate a new current generic buffer, and DMA the incoming data into the new current generic buffer. The TCP data placement may notify the TCP reassembler the starting TCP sequence number and the length of the new current generic buffer. Moreover, the TCP data placement may add entries into a TCP out-of-order table when the incoming data creates a new disjoint area. The TCP data placement may adjust an existing disjoint area to reflect any updates. When a TCP application allocates or posts a buffer, then the TCP reassembler may copy data from a linked list of generic buffers into posted buffers.

Abstract: Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate.

Abstract: Classifier for communication device. A communication device includes a classifier and a number of PHY (physical layer) receivers communicatively coupled thereto that enable the communication device to process various received signal types. Each of the PHY receivers is operable to perform pre-processing of a received frame (or packet) of data and to calculate a confidence level indicating whether the received frame is intended for that particular PHY receiver; this pre-processing does not involve processing (e.g., demodulation and/or decoding) of the received frame. Those PHY receivers having sufficiently high confidence levels assert claims to the classifier for the received frame. The classifier is operable to arbitrate between competing claims by 2 or more PHY receivers and to ensure that the received frame is provided to the PHY receiver for which it is intended.

Abstract: Apparatuses, methods, and systems for improved integrated circuit packages are described. An integrated circuit (IC) package includes a substrate having opposing first and second surfaces, an IC die, a plurality of conductive elements, and an encapsulating material. The substrate has a plurality of contact pads on the first surface that are electrically coupled to a plurality of electrically conductive features on the second surface. The plurality of conductive elements is formed on the first surface of the substrate. The IC die is located on the first surface of the substrate. The encapsulating material encapsulates the IC die and a portion of each element of the plurality of conductive elements.

Abstract: A system and method for processing information transport elements, such as ethernet packets, at interfaces to a forwarder. Modules that implement processing logic are allocated per interface and per direction (i.e., inbound or outbound). At any given interface, a series of modules would be used to process inbound packets; likewise, a set of modules would be used to process outbound packets. For inbound packets, the modules allocated for inbound processing are executed when the packet is received from the interface, before sending the packet on to the forwarder. For packets that are outbound from the forwarder, the modules allocated for outbound processing are applied when the packet is sent by the forwarder, prior to any other processing, e.g., queuing to hardware. To assign modules to different interfaces at a forwarder, a registration process is performed during the system start-up process, or dynamically at runtime.