Abstract: A method and apparatus for communicating between devices is described. In one embodiment, the method comprises detecting, at a switch, a presence of a first repeater coupled to the switch at a location, and automatically configuring the first repeater to enable the first repeater to communicate with a mobile station and the switch without using information resulting from a site survey of the location.

Abstract: Minimal hardware implementation of non-parity and parity trellis. More than one type of trellis can be represented using a minimal amount of hardware. In magnetic recording systems and other communication systems types, there is oftentimes a need to switch between trellises which support parity and ones which do not. Rules are presented herein which will ensure joint representation of more than one trellis while requiring minimal additional hardware when compared to representing only one trellis. To represent the non-parity trellis, emanating states, resultant states, and one or more expansion states (if needed) are all that is required. Any expansion states may also need to have its path metric and path memory corresponded to one of the resultant states to ensure proper detection according to the non-parity trellis.

Abstract: Certain embodiments for a self-booting Ethernet controller chip (NAC) may comprise a processor within the NAC that determines whether legacy boot code is present in memory external to the NAC. If legacy boot code is present in the external memory, the NAC may boot from the legacy boot code. If the legacy boot code is not present in the external memory, the processor may boot the NAC from the self-boot code in the ROM within the NAC. The processor may also read network configuration data from the external memory. The network configuration data may be stored, for example, in a NVRAM. The processor may copy the network configuration data from the NVRAM to a RAM within the NAC while booting.

Abstract: Noise-reduced pixels may be generated using outputs of filtering via a first filter and/or a second filter, and/or a blend of both outputs. Blending a current pixel and an output of filtering of current pixel via the first filter may generate a first blended current pixel. Filtering via the first filter may be based on the current pixel, a previous collocated pixel, and a next collocated pixel. Blending the current pixel and an output of filtering of current pixel via the second filter may generate a second blended current pixel. Filtering via the second filter may be based on the current pixel and a collocated pixel of the previous second blended video image or of the previous filtered output video image. Blending the first blended current pixel and the second blended current pixel using an adaptive blending factor may dynamically generate a filtered output pixel.

Abstract: Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit.

Abstract: True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

Abstract: Operating on video frames includes determining a frame set backdrop of a set of video frames that is a characterization of the relative difference in content of the set of video frames. Decreasing video quality of the set of video frames when the frame set backdrop is relatively higher indicating relatively greater content difference among video frames of the set of video frames and increasing/leaving quality of the set of video frames when the frame set backdrop is relatively lower indicating relatively lesser content difference among video frames of the set of video frames. Alteration of video quality of the set of video frames includes altering a frame rate, altering a pixel resolution, and/or altering color resolution of the set of video frames and/or altering a ratio of independent frames to predictive frames of the set of frames.

Abstract: A system and method for discovering a cable type and resistance for Power over Ethernet (PoE) applications. Cabling power loss in PoE applications is related to the resistance of the cable itself. A PHY can be designed to measure electrical characteristics (e.g., insertion loss, cross talk, length, etc.) of the Ethernet cable to enable determination of the cable resistance. The determined resistance can be used in powering decisions and in adjusting power budgets allocated to power source equipment ports.

Abstract: A universal serial bus (USB) dongle device includes a GPS receiver that receives a GPS signal and that generates GPS data in response thereto. A USB plug is connectable to a host device. A USB controller circuit formats the GPS data in the USB format for communication to the host device. A millimeter wave interface includes a first millimeter wave transceiver coupled to the wireless transceiver and a second millimeter wave transceiver coupled to the USB controller circuit that wirelessly communicates the GPS data between the GPS receiver and the USB controller circuit via signaling in a millimeter wave frequency band.

Abstract: A video gaming device includes a processing module, a graphics processing module, and a video gaming object interface module. The processing module interprets a digital image(s) of a player to determine an identity of the player. When the identity of the player is determined, the processing module retrieves a user profile and generates video gaming menu data in accordance with at least one data element of the user profile. The graphics processing module renders a display image based on the video gaming menu. The video gaming object interface module receives a wireless menu selection signal and converts it into a menu selection signal.

Abstract: In a DOCSIS based satellite gateway data is transmitted over a single downstream channel, at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. To accomplish this, the downstream DOCSIS MAC data is parsed to extract DOCSIS packets. The DOCSIS packets are then loaded into packet queues based on an identifier within such packets such as the MAC destination address or SID. Each of the queues represents a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers based on the current signal quality being experienced at the subscriber location. A PHY-MAP describing the downstream data structure to be transmitted and inserted into the downstream data. Data is extracted from the packet queues in queue blocks as defined by the PHY-MAP.

Abstract: An apparatus and method is disclosed for adjusting a gain of an amplifier assembly array. The amplifier assembly array includes a first stage to provide an amplified signal based upon an input signal. The first stage has a variable gain controlled in response to one or more gain control signals. An Automatic Gain Control (AGC) module generates the one or more gain control signals according to a ramp function in response to a power level of the amplified signal. The first stage may include a first low noise amplifier (LNA) to amplify the input signal to provide a first amplified input signal and a second LNA to amplify a second input signal to provide a second amplified signal. A switch selects between the amplified signal and the second amplified signal to provide the amplified signal. The amplifier assembly array may additionally include a second stage to provide a second amplified signal based upon the amplified signal.

Abstract: A voice data and RF integrated circuit (IC) includes a driver that generates an RF signal to a power amplifier module from an up-converted signal. A modulation controller provides a first modulation signal to the driver for modulating the up-converted signal when a modulation control signal has a first value and provides a second modulation signal to the power amplifier module for modulating the RF signal when the modulation control signal has a second value.

Abstract: Aspects of a method and system for signal generation via a PLL with a DDFS feedback path are provided. In this regard, a phase difference between a reference signal and a feedback signal may be utilized to control a VCO, wherein the feedback signal is generated by a DDFS. Voltage, current and/or power levels of the generated feedback signal may be limited to a determined range of values. Moreover, the feedback signal may be based on an output of the VCO and a digital control word input to the DDFS. The digital control word may be programmatically controlled by, for example, a processor. Additionally, the control word may be determined based on a desired frequency of the generated feedback signal and a desired output frequency of the VCO. Accordingly, the DDFS may be clocked by the output of the VCO, or by a divided down version of the VCO output.

Abstract: A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes time domain training symbols and time domain data symbols. The baseband processing module includes a channel estimator operable to process the time domain training symbols to produce a time domain channel estimate, a Fast Fourier Transformer operable to convert the time domain channel estimate to the frequency domain to produce a frequency domain channel estimate, a weight calculator operable to produce frequency domain equalizer coefficients based upon the frequency domain channel estimate, an Inverse Fast Fourier Transformer operable to converting the frequency domain equalizer coefficients to the time domain to produce time domain equalizer coefficients, and an equalizer operable to equalize the time domain data symbols using the time domain equalizer coefficients.

Abstract: A filter settings generation operation includes sampling colored noise present at the input of a receiver to produce a sampled signal. The sampled signal is spectrally characterized across a frequency band of interest to produce a spectral characterization of the sampled signal. This spectral characterization may not include a signal of interest. The spectral characterization is then modified to produce a modified spectral characterization. Filter settings are then generated based upon the modified spectral characterization. Finally, the input present at the receiver is filtered using the filter settings when the signal of interest is present to whiten colored noise that is present with the signal of interest. In modifying the spectral characterization, pluralities of spectral components of the spectral characterization are independently modified to produce the modified spectral characterization. Modifications to the spectral characterization may be performed in the frequency domain and/or the time domain.

Abstract: Typical communication systems operate with a single channel decoder, and hence would have to settle for the performance from the single channel decoder regardless of the conditions of the communications channel. The present invention uses a hybrid channel decoder comprising multiple channel decoders, each configured to optimize the quality of the re-constructed signal for different channel conditions. Therefore, the desired decoder can be selected as conditions of the communications channel, or the data signal, change over time, so as to optimize the re-constructed data signal. In embodiments, the data signal is a speech signal.

Abstract: Certain aspects of a method and system for transparent transmission control protocol (TCP) offload are disclosed. Aspects of a method may include collecting TCP segments in a network interface card (NIC) processor without transferring state information to a host system. The collected TCP segments may be buffered in a coalescer. The coalescer may verify that the network flow associated with the collected TCP segments has an entry in a flow lookup table (FLT). When the FLT is full, the coalescer may close a current entry and assign the network flow to the available entry. The coalescer may also update information in the FLT. When an event occurs that terminates the collection of TCP segments, the coalescer may generate a single aggregated TCP segment based on the collected TCP segments. The aggregated TCP segment and state information may be communicated to the host system for processing.

Abstract: The present invention provides a equalizer processing module operable to cancel interference associated with received radio frequency (RF) burst(s). This equalizer processing module includes a first equalizer processing branch and an optional second equalizer processing branch. The first equalizer processing branch is operable to be trained by applying a recursive DMI process such as a Levison algorithm, based upon known training sequences and equalize the received RF burst. This results in soft samples or decisions which in turn may be converted to data bits. The soft samples are processed with a de-interleaver and channel decoder, where the combination is operable to produce a decoded frame of data bits from the soft samples. This allows interfering signals to be cancelled and more accurate processing of the received RF bursts to occur.

Abstract: Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate.