Abstract: A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.

Abstract: A method for operating in a network that includes one or more of the following: assigning a respective active member address to each of a plurality of first slave nodes participating in a piconet; receiving a request to join the piconet; determining that no more different active member address are available in the piconet; determining that a second slave node supports extended addressing; and performing calculations as a function of the bandwidth requirements of the second slave node to determine whether to share an assigned active member address with the second slave node.

Abstract: A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.

Abstract: An integrated circuit radio transceiver and method therefor includes capacitive loop filter with selectable capacitive elements that are operable to adjust a signal level provided to a voltage controlled oscillator to control a frequency of an output signal of the oscillator. A plurality of switches are controlled by logic to define a discharge mode, a charge mode and charge sharing mode in which a plurality of capacitive elements share charge while generating the input voltage to the oscillator.

Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.

Abstract: The invention decreases phase distortion in a transmitter by balancing C load in the power amplifier input such that a PGA won't have phase distortion.

Abstract: An offset cancellation scheme in which offset cancellation current is sourced into one differential branch of a driver circuit and sinked from the opposite differential branch. The source/sink arrangement allows for offset cancellation current to be introduced into the circuit, but the overall total average current remains substantially unchanged. When used in an I and Q mixer circuits, the offsets may be canceled without generating an I/Q imbalance in the I and Q mixers.

Abstract: A universal serial bus (USB) dongle device includes a wireless telephony transceiver that receives an inbound RF signal and that generates inbound data based on the inbound RF signal and receives outbound data and that generates an outbound RF signal in response thereto. A USB plug is connectable to a host device. A USB controller circuit formats the inbound data in the USB format for communication to the host device and to recover the outbound data from outbound data received in the USB format from the host device. A millimeter wave interface includes a first millimeter wave transceiver coupled to the wireless transceiver and a second millimeter wave transceiver coupled to the USB controller circuit that wirelessly communicates the inbound data and the outbound data between the wireless telephony receiver and the USB controller circuit.

Abstract: A system and method for synchronizing translation lookaside buffer (TLB) access in a multithread processor is disclosed. When a first exception is found while searching the TLB, the exception is handled. While the exception is handled, thread processors are restricted from requesting the handling of any other exception.

Abstract: Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.

Abstract: An ESD protection circuit for a transistor having a drain and source coupled to high-speed signaling pins of an integrated circuit includes a first string of clamping elements and a second string of clamping elements. The first string of clamping elements has a collective capacitance less than the capacitance of a single clamping element. The first string of clamping elements is operably coupled to the drain and source of the transistor and conducts when a first polarity ESD voltage is applied to the high-speed pins. The second string of clamping elements has a collective capacitance less than the capacitance of one clamping element. The second string of clamping elements is operably coupled to the drain and source of the transistor and conducts when a second polarity ESD voltage is applied to the high speed signaling pins.

Abstract: A Radio Frequency (RF) transceiver includes a first RF transceiver group, a second RF transceiver group, local oscillation circuitry, and calibration control circuitry. Each of the RF transceiver group has an RF transmitter and an RF receiver. The local oscillation circuitry selectively produces a local oscillation to the first RF transceiver group and to the second RF transceiver group. The calibration control circuitry is operable to initiate calibration operations including transmitter self calibration operations, first loopback calibration operations, and second loopback calibration operations. During loopback calibration operations, test signals produced by an RF transceiver group are looped back to an RF receiver of another RF transceiver group.

Abstract: Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e.g., all 1st columns in 1 or more sub-matrices, all 2nd columns in 1 or more sub-matrices, etc.). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e.g., all 1st rows in 1 or more sub-matrices, all 2nd rows in 1 or more sub-matrices, etc.).

Abstract: Presented herein is a system, method, and apparatus for firmware code-coverage in complex system on chip. A circuit for analyzing code coverage of firmware by test inputs comprises an input and a memory. The input receives an address from a code address bus. The memory stores recorded addresses from the code address bus. The memory comprises a plurality of memory locations, each of the memory locations mapped to a particular one of a corresponding plurality of addresses associated with the firmware. The contents of the memory location associated with the address received from the code address bus being incremented responsive to receipt of the address.

Abstract: A method and system for bits and coding assignment utilizing Eigen beamforming with fixed rates for a closed loop WLAN is provided. Aspects of the method for communicating information in a communication system may comprise transmitting data via a plurality of radio frequency (RF) channels utilizing a plurality of transmitting antennas and receiving feedback information related to the plurality of RF channels. Bits may be assigned for transmission via at least one of the plurality of RF channels based on the feedback information. At least a portion of subsequent data having at least a first coding rate based on the assignment of bits may be transmitted via at least one of the plurality of RF channels. The method may also comprise receiving data via a plurality of RF channels utilizing a plurality of receiving antennas, and transmitting feedback information related to the plurality of RF channels.

Abstract: Algebraic method to construct LDPC (Low Density Parity Check) codes with parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. A novel approach is presented by which identity sub-matrices undergo cyclic shifting, thereby generating CSI sub-matrices that are arranged forming a parity check matrix of an LDPC code. The parity check matrix of the LDPC code may correspond to a regular LDPC code, or the parity check matrix of the LDPC code may undergo further modification to transform it to that of an irregular LDPC code. The parity check matrix of the LDPC code may be partitioned into 2 sub-matrices such that one of these 2 sub-matrices is transformed to be a block dual diagonal matrix; the other of these 2 sub-matrices may be modified using a variety of means, including the density evolution approach, to ensure the desired bit and check degrees of the irregular LDPC code.

Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.

Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.

Abstract: Various example implementations are disclosed. According to one example, an integrated circuit may include a key extractor, a translation table block, and a memory assigner. The key extractor may be configured to receive data, extract key-related information from the data, and send the key-related information to a first memory device. The translation table block may be configured to update a mapping table based on a memory assigner assigning physical portions of the first memory device to each of a plurality of address types, receive an index from the first memory device in response to the key extractor sending the key-related information to the first memory device, and send a data request to a second memory device based on the received index, the data request identifying a physical portion of the second memory device.

Abstract: According to an example embodiment, an apparatus may include a non-Universal Serial Bus (non-USB) serial interface, a USB connector, a first protection circuit connected between a first data connection of the non-USB serial interface and a first data connection of the USB connector, a second protection circuit connected between a second data connection of the non-USB serial interface and a second data connection of the USB connector, a processor, and a detection circuit connected to the second data connection of the USB connector, the detection circuit configured to output a signal to the processor indicating an attachment or connection of a second non-USB serial interface to the USB connector.