Abstract: An active splitter circuit arrangement includes a first amplification module having a number of first input ports and first output ports. The first amplification module is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals, each substantially matching the input signal. Also included is a first gain control device having a number of gain input ports respectively coupled to the first output ports and a gain output port coupled to at least one of the first input ports. The first gain control device is configured to control a gain of the first amplification module. Next, a number of second amplification modules corresponding to the number of output signals has a number of second input ports respectively coupled to the first output ports.

Abstract: A circuit and method therefor provides programmable digital delay that is produced to introduces a delay in either an envelope or a phase signal path of an RF polar transmitter in order to eliminate the delay mismatch between the two paths. For two signal paths, a faster signal may be delayed by a digital processor or a slower signal may be transmitted early so that signals in the two signal paths arrive at a specified circuit node in synchronization. Timing shift may be implemented in either the envelope signal path or the phase signal path and may be used to reduce or increase the timing of a signal path.

Abstract: A game device includes a first receiver that receives body motion signals from a plurality of remote motion sensing device coupled to a user's body. A user data generation module generates simulated body image data. A processor executes a game application that generates display signals for display on a display device, wherein the display signals are generated based on the simulated body image data.

Abstract: An integrated circuit containing multiple modules coupled to a pad via a multiplexer. The modules are selectively coupled to the pad by the multiplexer to provide integrated circuit function flexibility with a limited number of pads. A multiplexer select signal determines which module or clock circuit is coupled by the multiplexer. A common buffer may be coupled between the multiplexer and the pad to save substrate space. An analog circuit may be coupled to the pad to provide a signal path minimizing signal distortion. The integrated circuit's clock may be coupled via the multiplexer to an off-substrate circuit. Selective module coupling improves the integrated circuit's testing speed, may salvage an integrated circuit containing a malfunctioning module, and provides for signal loopback during testing.

Abstract: A system and method for processing information transport elements, such as ethernet packets, at interfaces to a forwarder. Modules that implement processing logic are allocated per interface and per direction (i.e., inbound or outbound). At any given interface, a series of modules would be used to process inbound packets; likewise, a set of modules would be used to process outbound packets. For inbound packets, the modules allocated for inbound processing are executed when the packet is received from the interface, before sending the packet on to the forwarder. For packets that are outbound from the forwarder, the modules allocated for outbound processing are applied when the packet is sent by the forwarder, prior to any other processing, e.g., queuing to hardware. To assign modules to different interfaces at a forwarder, a registration process is performed during the system start-up process, or dynamically at runtime.

Abstract: A method for estimating electrical length of a loop in a digital subscriber line (DSL) system begins by estimating an electrical length of a loop for each of a plurality signals based on a known power level of the plurality of signals, a known frequency for each of the plurality of signals, and a received power level for each of the plurality of signals. The method continues by processing the plurality of estimated electrical lengths in accordance with a function corresponding to characteristics of the loop to produce a determined electrical length.

Abstract: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout.

Abstract: A method and system for increasing the efficiency of providing bandwidth for voice traffic to a data provider via wireless communication mediums is provided. This is generally accomplished by not transmitting any data during the silence periods and playing out background noise (i.e., comfort noise) at the other end, to obtain significant bandwidth savings.

Abstract: Methods and systems for processing an encoded video stream are disclosed. Aspects of the method may comprise generating a plurality of temporal or spatial prediction pixels based on mode information within the encoded video stream. A plurality of prediction errors may be generated from a plurality of quantized frequency coefficients generated from the encoded video stream. At least one current macroblock may be generated using the generated plurality of temporal or spatial prediction pixels based on the generated plurality of prediction errors. The encoded video stream may be symbol interpreted using context adaptive variable length coding and/or context adaptive binary arithmetic coding. The encoded video stream may be buffered prior to the symbol interpretation. The plurality of quantized frequency coefficients may be generated from the encoded video stream. If the encoded video stream comprises temporal prediction mode information, the plurality of temporal prediction pixels may be generated.

Abstract: The invention refers to a video data processing system and a video data processing circuit, comprising at least two functional blocks of which at least a first functional block is programmable so that different functions can be provided by said first functional block.

Abstract: A traffic prioritization system performs a coarse classification of upstream bursts at the physical interface of a headend communications device. The headend device monitors and controls communications with a plurality of remote communications devices throughout a widely distributed network, including the Internet. The traffic prioritization system includes a burst receiver that receives and sends the upstream bursts to a classifier. At an appropriate time, the classifier receives the upstream bursts and queries a priority lookup table (LUT) to determine a priority classification. The priority classification is used to separate the bursts into two or more priority levels. The higher priority level is used to designate services having a low tolerance for delay, such as telephony. Upon classification, the upstream bursts are forwarded to one of several priority queues. Each priority queue corresponds to at least one priority level.

Abstract: A technique is provided for limiting distortion of an audio signal being processed for playback by an audio device. In accordance with the technique, the audio signal is compressed to generate a compressed audio signal having a level that does not exceed a compression limit. The compressed audio signal is then soft clipped signal to generate a soft-clipped audio signal having a level that does not exceed a soft clipping limit, wherein the compression limit exceeds the soft clipping limit. The technique may also include passing the audio signal through a shaping filter prior to compressing the audio signal, wherein passing the audio signal through a shaping filter comprises modifying the level of selected frequency components of the audio signal.

Abstract: A system for detecting a key with key debounce including a circuit for detecting a key activation; a first counter coupled to the circuit and a clock for testing the key activation for a first user definable number of clock cycles; a key debounce buffer for storing a key index identifying the activated key, if the key activation is valid for the first user definable number of clock cycles; a second counter for testing the identified activated key for a first user definable number of hardware key scan cycles; and a key event buffer for storing a key activation event, if the key activation is valid for the first user definable number of hardware key scan cycles.

Abstract: A second output transmission signal (“TX2”) added to a line driver is a scaled version of the main output transmission signal (“TX1”). TX2 is scaled from TX1 by a variable scale factor K. An adaptive hybrid circuit subtracts TX1 and TX2 from a line signal carrying both a line transmission signal and a line received signal (“RX”). A programmable impedance Ztune is coupled between the TX2 output of the line driver and the RX output of the adaptive hybrid circuit. A transmission echo in the output RX signal is measured. K and Ztune are then adaptively tuned to minimize the transmission echo. The hybrid in this case becomes a 4-port network, one port specifically added to adaptively cancel the transmission echo in the RX output of the adaptive hybrid circuit. Alternatively, the hybrid may be a 3-port hybrid including variable impedances to cancel the line transmission signal.

Abstract: A system (50) includes a communication path (170) and transmits data on a network (103, 106). A transmitter (101) transmits data on the network and a receiver (112) receives data from the network. A component (102, 114) in the communication path has a transfer characteristic (C1, C2, C3) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.

Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.

Abstract: An integrated circuit (IC) package is provided. The IC package includes a substantially planar substrate having a plurality of contact pads on a first surface electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate, an IC die having a first surface mounted to the first surface of the substrate, and a heat sink assembly coupled to a second surface of the IC die and to a first contact pad on the first surface of the substrate to provide a thermal path from the IC die to the first surface of the substrate. The IC die has a plurality of I/O pads electrically connected to the plurality of contact pads on the first surface of the substrate. The IC die is mounted to the first surface of the substrate in a flip chip orientation.

Abstract: A supervisory communications system (such as, a headend cable modem termination system) manages communications with a plurality of remote communications devices (such as, a cable modem). The supervisory system enables each of its physical channels to have multiple logical channels, with each logical channel having differing channel parameters or operating characteristics. As a result, different types of communication devices are permitted to coexist on the same physical spectrum. In other words, a communications device using, for example, spread spectrum modulation technologies require different operating characteristics than a communications device using, for example, time division multiplexing technologies.

Abstract: A minimal leakage power Standard Cell Library is provided. The minimal leakage power Standard Cell Library provides minimal leakage power cells with improved speed characteristics. The minimal leakage power Standard Cell Library includes cells from an existing Standard Cell Library and a set of minimal leakage power cells for a selected set of logic functions. The minimal leakage power Standard Cell Library is formed by identifying a set of logic functions. For each logic function in the identified set, a base case for an unfolded implementation of the logic function is determined. Widths for transistors in a transistor topology used in the unfolded implementation of the logic function are determined based on the non-linear leakage power characteristics for the transistor topology to achieve minimal leakage power. The determined widths are then assigned to the transistors and the minimal leakage cell is added to the library.

Abstract: A circuit provides a digital signal at optimal times to a digital processor of a transmitter. The circuit includes a complex analog-to-digital converter (ADC), a demodulator and a timing recovery circuit. The complex ADC is connected to receive an analog complex modulated baseband signal and to convert the analog complex modulated baseband signal to a digital complex modulated baseband signal. The demodulator operates to demodulate the digital signal to produce a demodulated digital signal for input to the digital processor. The timing recovery circuit receives a control signal and activates the digital processor based on a fixed timing relationship between receipt of the control signal at the timing recovery circuit and receipt of the analog complex modulated baseband signal at the complex ADC.