Abstract: Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function call causes the cryptography accelerator to execute multiple cryptographic operations in a manner tailored for specific processing steps, such as steps during a handshake phase of a secured session. The techniques provide efficient use of hardware processing resources, data interfaces, and memory interfaces.

Abstract: A method and system for configurable drain for two-way handshake system is provided and may comprise coupling a transmitting device to a drain bucket, and draining unwanted data at the transmitting device. The drain bucket may be configurably coupled to the transmitting device via a switch, where the switch may be a crossbar switch. The drain bucket may receive at least one transmitter handshake signal from at least one transmitting device. The drain bucket may transmit at least one receiver handshake signal to the at least one transmitting device. The receiver handshake signal may be asserted at least as long as the received transmitter handshake signal is asserted. The receiver handshake signal may be based on the received transmitter handshake signal. For example, the received transmitter handshake signal may be looped back by the receiver as the receiver handshake signal.

Abstract: A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing pipeline's front end comprises an array for storing at least two condition bits, the condition bits being adapted for indicating respective conditions. The front end is adapted for resolving conditional branch instructions by accessing the array of condition bits whenever a conditional branch instruction occurs, the respective branch instruction being resolved in accordance with a corresponding condition bit. In another embodiment, the condition bits are combined with predicated execution of instructions, with the instruction's predicates being evaluated at the processing pipeline's back end.

Abstract: Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.

Abstract: Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading. A novel approach is presented by which adjustable amplification and equalizer may be achieved using a C3MOS wideband data stage. This may be referred to as a C3MOS wideband data amplifier/equalizer circuit. This employs a wideband differential transistor pair that is fed using two separate transistor current sources. A switchable RC network is communicatively coupled between the sources of the individual transistors of the wideband differential transistor pair. There are a variety of means by which the switchable RC network may be implemented, including using a plurality of components (e.g., capacitors and resistors connected in parallel).

Abstract: The present invention provides apparatus and methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS rule verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, one or more bits are suppressed in the payload header and a the payload header suppressed and a payload header suppression index is added to the suppressed packet payload header. Following transmission, the suppression indexed is used to identify the bits to be reinserted into the suppressed payload header.

Abstract: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

Abstract: Successive interference canceling for CDMA. ICI may result from a signal's multi-path effects, or by filtering/suppression of some of the component energy of the signaling waveforms. Energy component attenuation destroys orthogonality of CDMA symbols thereby causing ICI. An ICF suppresses frequency domain portions(attenuates ingress), but also introduces ICI. Following the ICF, the signal is de-spread sliced, re-spread and convolved with the ICF echoes (except first tap echoes). Convolving re-spread hard decisions with delayed ICF taps is equivalent to partially re-modulating the first-pass hard decisions to efficiently “add-back-in” the signal energy which was blanked/subtracted by the ICF. Alternatively, parameter estimation de-rotates and re-rotates soft symbols and hard decisions, respectively, compensating for undesirable symbol rotation. The convolved signal is subtracted from a delayed version of the ICF output signal.

Abstract: In RF transceivers, a method and a system for a frequency feedback adjustment in digital receivers are provided. A DC offset may result from the difference in frequencies between an RF transmitter and an RF receiver. An adjustment of the receiver's frequency may be implemented after synchronization occurs and may be performed by utilizing the Forward Error Correction (FEC) repetition rate in a header of a Bluetooth packet. The adjustment may be performed when the frequency difference exceeds a threshold value. In another aspect, adjusting the frequency of the RF receiver may be performed by modifying and/or changing a phase locked loop (PLL) trimmer register. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip uses window descriptors to describe logical surfaces, or windows, of graphics information to be displayed on the screen. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided.

Abstract: The invention provides a system and method for updating software in the CPU of a network device without interrupting the operation of the network device. The invention determines whether operating state information is recoverable. If it is not recoverable, then it will be stored in a metadata module or reload buffer. When the CPU is rebooted, after a software update or crash, it operates in a special reload mode and is able to recover any system state information not available in the network device from the metadata module.

Abstract: Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been generated using combined LDPC coding and modulation encoding to generate LDPC coded modulation signals. In addition, the bit metric updating is also extendible to decoding of LDPC variable code rate and/or variable modulation signals whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. By ensuring that the bit metrics are updated during the various iterations of the iterative decoding processing, a higher performance can be achieved than when the bit metrics remain as fixed values during the iterative decoding processing.

Abstract: A charge pump circuit that supplies current to an offset current of an output signal for an oscillating circuit is disclosed. The charge pump circuit includes a first switch and a second switch. The first switch is coupled to a gate of an output diode that provides a charge up current from the charge pump circuit. A second switch is coupled to an anode of the output diode and supplies the charge up current to the output diode. The first switch comprises a first state and the second switch comprises a second state that is opposite the first state. Thus, when the second switch is on, the first switch is off. The charge pump circuit also includes a capacitance to hold a bias voltage when the first switch is off.

Abstract: In a transmitter that includes a plurality of partitioned DAC processing cells coupled to a corresponding plurality of partitioned encoder processing cells, a method for processing signals may include aggregating outputs of each of the plurality of partitioned DAC processing cells to generate an analog output signal. The transmitter may be a direct drive transmitter. The generated analog output signal may be a reduced emissions analog signal. The plurality of encoder processing cells may be partitioned into at least a group of odd encoder processing cells and a group of even encoder processing cells. The plurality of DAC processing cells may be partitioned into at least a group of odd DAC processing cells for processing outputs of the group of odd encoder processing cells and a group of even DAC processing cells for processing outputs of the group of even encoder processing cells.

Abstract: Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.

Abstract: Transmitting streamed video to at least one wireless terminal by a wireless network having a channel frequency reuse pattern. The wireless network receives a request for the streamed video from the at least one wireless terminal and receives position information from the at least one wireless terminal requesting the streamed video. The wireless network selects a transceiving device to service transmission of the streamed video to the at least one wireless terminal. The transceiving device is allocated a first channel frequency set of the channel frequency reuse pattern. The wireless network or a component thereof selects a channel from a second channel frequency set that is different from the first channel frequency set. The transceiving device then, using a directional antenna, transmits the streamed video to the at least one wireless terminal in a direction based upon the position information using the selected channel.

Abstract: A Bluetooth host solves the aforementioned problems by evaluating a Bluetooth service provider server ID and by determining which of a plurality of access IDs map to the server ID and, correspondingly, providing a Bluetooth access ID that corresponds thereto. Accordingly, one Bluetooth host may readily gain access to any one of a plurality of different devices and different types of devices. Additionally, the Bluetooth host includes capacity to store and provide additional supporting information according to the type of device that is the Bluetooth service provider. Generally, the Bluetooth host stores a plurality of access or link IDs in relation to a plurality of master device IDs and, upon detecting a beacon, determines what access or link ID to provide and whether to provide additional stored information.

Abstract: Improved apparatus for a radio communication system having a multiplicity of mobile transceiver units selectively in communication with a plurality of base transceiver units which, in turn, communicate with one or more host computers for storage and manipulation of data collected by bar code scanners or other collection means associated with the mobile transceiver units. A network controller and an adapter which has a simulcast and sequential mode provide selective interface between host computers and base transceivers. A scheme for routing data through the communication system is also disclosed wherein the intermediate base stations are organized into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically.

Abstract: A communication system includes a first device and a second device that can advertise multiple capabilities using communication links. A first type of auto-negotiation between the first and second devices is performed using a first communication link between the devices. A second communication link between the devices is used to facilitate a second type of auto-negotiation. For example, the first communication link can include pairs A and B of an IEEE Std. 802.3 four twisted pair cable. The second communication link can include pairs C and D of the cable.

Abstract: According to one exemplary embodiment, a method of preventing harmonics from causing distortion in a communications system includes feeding a test signal through a pre-distortion circuit in the communications system to a transmitter in the communications system. The method continues by transmitting a distorted output signal produced by the transmitter to an analyzer, analyzing the distorted output signal to identify one or more undesired harmonics, and generating and sending calibration data from the analyzer to calibrate the pre-distortion circuit, thereby preventing the one or more undesired harmonics from causing distortion in the communications system. In one embodiment, a system to prevent harmonics from causing distortion in a communications system includes a pre-distortion circuit, a transmitter, and an analyzer configured to identify one or more undesired harmonics and to generate and send calibration data to prevent the undesired harmonics from causing distortion.