Abstract: The wide bandwidth transceiver includes a receiver section, a transmitter section, and a local oscillation module. The local oscillation module generates a first and a second local oscillation. The transmitter section converts an outbound baseband signal and/or a low intermediate frequency (IF) signal into a first outbound radio frequency (RF) signal based on the second local oscillation when the wide bandwidth transceiver is in a second wireless standard mode and converts the outbound baseband and/or the low IF signal into a second outbound RF signal based on the first and second local oscillations when the wide bandwidth transceiver is in a first wireless standard mode.

Abstract: A method and computer program product for providing RTP suppression across a DOCSIS network. An index number and a set of rules are sent to a receiver. The index number indicates the type of header suppression technique (i.e., RTP header suppression) to be performed, and the set of rules define how to recreate the RTP packets on the receiving end. At least one complete RTP packet is transmitted upstream for enabling a receiver to learn the RTP header. Subsequent RTP packets are transmitted upstream for reconstruction at the receiving end. The subsequent RTP packets are comprised of delta values representing fields that dynamically change from packet to packet in an RTP header.

Abstract: A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).

Abstract: The system and method for adaptive flow control transmits pause off packets to network nodes after a calculated time based on switch resource usage thereby alleviating congestion is a network switching system. The method includes measuring a resource usage level in a network switching system, incrementing a register based on the measurement if the measurement exceeds a predetermined level, decrementing the register at a constant rate, and generating a pause off packet when the register is decremented to or below a pre-specified level.

Abstract: A method and system for processing a data flow in a multi-channel, multi-service environment is described. In one embodiment, a socket is dynamically allocated, the socket including a dynamically allocated service. Further, the server processes the data flow based upon the type of data being processed.

Abstract: A method to detect an event between a data source and a data sink using a trigger core is described herein. The method comprises monitoring control lines and an associated data stream for a programmable pattern, wherein the pattern is one or more of a condition, state or event. The method further comprises generating an indication by updating a status register, sending an interrupt or asserting a control line upon a pattern match.

Abstract: A method and system to transfer a data stream from a data source to a data sink are described herein. The system comprises a trigger core, a plurality of dedicated buffers and a plurality of dedicated buses coupled to the plurality of buffers, trigger core, the data source and the data sink. In response to receiving a request for a data transfer from a data source to a data sink, the trigger core assigns a first buffer and a first bus to the data source for writing data, locks the first buffer and first bus, releases the first buffer and the first bus upon indication from the data source of completion of data transfer to the first buffer, assigns the first buffer and first bus to the data sink for reading data and assigns a second buffer and second bus to the data source for writing data thereby pipelining the data transfer from the data source to the data sink.

Abstract: Systems, methods, and computer program products that can be used concurrently or alternatively to detect errors in data as well as to protect access to data are provided. Embodiments enable a coherent data set (CDS) which is a data set guaranteed to be genuine and error-free at run-time. Embodiments provide systems, methods, and computer program programs to create a CDS, identify a CDS, and verify the coherency of a data set purported to be a CDS. Embodiments further enable privileged functions which are functions that can only be accessed by a restricted set of other privileged functions. Embodiments provide systems, methods, and computer program products to create, identify, and protect access to privileged functions.

Abstract: A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers configured to receive a plurality of input differential signals having different phases, and configured to generate a plurality of weighted signals responsive to the plurality of input differential signals. A plurality of digital-to-analog converters (DAC) are arranged into a plurality of groups, each group of DACs configured to provide current for one of the corresponding differential amplifiers. The number of active DACs in each group of DACs determines a relative weighting of the weighted signals, where relative weighting determining an output phase of an output signal of the phase rotator. The DACs are configured to adjust the output phase of the phase rotator. At a kth phase, N/4 adjacent DACs are activated that are indexed as m0, m1, . . . m((N/4)?1), wherein N is the number of said plurality of DACs.

Abstract: A system and method for continual cable thermal monitoring using cable resistance considerations for Power over Ethernet (PoE) applications. Cable heating in PoE applications is related to the resistance of the cable itself. By periodically monitoring the resistance of the cable, it can be determined whether the cable has exceeded certain operating thresholds. The determined resistance as a proxy for cable heating can then be used in adjusting operational characteristics of PoE channels.

Abstract: A method and system to transfer data from one or more data sources to one or more data sinks using a pipelined buffer interconnect fabric is described.

Abstract: Methods and apparatus for dual hash tables are disclosed. An example method includes logically dividing a hash table data structure into a first hash table and a second hash table, where the first hash table and the second hash table are substantially logically equivalent. The example method further includes receiving a key and a corresponding data value, applying a first hash function to the key to produce a first index to a first bucket in the first hash table, and applying a second hash function to the key to produce a second index to a second bucket in the second hash table. In the example method the key and the data value are inserted in one of the first hash table and the second hash table based on the first index and the second index.

Abstract: A MIMO transceiver integrated circuit (IC) includes a plurality of multiple band direct conversion transmitter sections, a plurality of multiple band direct conversion receiver sections, and a local oscillation generation module. Each of the plurality of multiple band direct conversion transmitter sections includes a transmit baseband module and a multiple frequency band transmission module. Each of the plurality of multiple band direct conversion receiver sections includes a multiple frequency band reception module and a receiver baseband module. The local oscillation generation module is operably coupled to generate the first frequency band local oscillation when the multiple band MIMO transceiver IC is in a first mode and operably coupled to generate the second frequency band local oscillation when the multiple band MIMO transceiver IC is in a second mode.

Abstract: A computer program product comprising a computer useable medium including control logic stored therein to transfer data from a data source to a data sink is described herein.

Abstract: Systems, methods, and computer program products that can be used concurrently or alternatively to detect errors in data as well as to protect access to data are provided. Embodiments enable a coherent data set (CDS) which is a data set guaranteed to be genuine and error-free at run-time. Embodiments provide systems, methods, and computer program programs to create a CDS, identify a CDS, and verify the coherency of a data set purported to be a CDS. Embodiments further enable privileged functions which are functions that can only be accessed by a restricted set of other privileged functions. Embodiments provide systems, methods, and computer program products to create, identify, and protect access to privileged functions.

Abstract: An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.

Abstract: A Wireless Access Point (WAP) of a Wireless Local Area Network (WLAN) infrastructure includes a processor, a radio and a directional antenna. The radio supports communications with a first plurality of wireless terminals and listens to, but does not participate in transmissions of at least some of a second plurality of wireless terminals to collect non-participatory WAP data. Based upon the non-participatory WAP data, the processor creates WAP operational reports and provides the WAPs operational reports to the WLAN. The WLAN creates directions based thereon and directs the WAP to alter the gain pattern of the directional antenna.

Abstract: A method for synchronizing clocks in a packet transport network. The method comprises, receiving an external network clock at a central packet network node and transmitting timing information to a plurality of packet network devices, the timing information based upon the external network clock. The method further comprises, transmitting and receiving data that is synchronized to the timing information to a plurality of connected packet network devices. And finally, delivery of packets to an external interface via a packet network that contains data synchronized to the external network clock.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: A low pass filter includes a switchable resistor bank, a gain stage, and a capacitor bank. The resistors and capacitors switched into the circuit determine a cutoff frequency of the low pass filter. Frequency programmability may be obtained using the switchable resistor bank implemented as a parallel bank of binary weighted resistors. Further frequency programmability may be obtained using the switchable capacitor bank in conjunction with the switchable resistor bank. The resistor and capacitor processes in a semiconductor wafer are sufficiently accurate and repeatable so as to minimize any necessary calibration.