Patents Assigned to Bull, S.A.
  • Patent number: 9921810
    Abstract: An object class (Class1) in a computer system is dynamically created by creating a global generic class (GenericClass) having two possible members, wherein at least one member is an instance of a generic class (GenericAttribute, GenericMethod), and by instantiating the global generic class.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: March 20, 2018
    Assignee: BULL S.A.S.
    Inventors: Armand Nachef, Gerard Sitbon
  • Patent number: 9507606
    Abstract: An object class (Class1) in a computer system is dynamically created by creating a global generic class (GenericClass) having two possible members, wherein at least one member is an instance of a generic class (GenericAttribute, GenericMethod), and by instantiating the global generic class.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: November 29, 2016
    Assignee: BULL S.A.S.
    Inventors: Armand Nachef, Gérard Sitbon
  • Publication number: 20140108262
    Abstract: A method for providing privacy in online transactions. The method can include receiving, at a service provider system, a purchase request from a client, the purchase request including banking information, and the banking information being encrypted with a third party public key such that the service provider system cannot decrypt the encrypted banking information. The encrypted banking information can be transmitted to a bank system, such that the banking information cannot be used to identify the identity of the client. The method can also include receiving an authorization message if the client's purchase request is authorized.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 17, 2014
    Applicants: LABORATOIRE GREYC, BULL S.A.S.
    Inventors: Aude PLATEAUX, Vincent COQUET, Sylvain VERNOIS, Patrick LACHARME, Christophe ROSENBERGER
  • Patent number: 8627406
    Abstract: A security and protection device (1) for protection of the data and executable codes of any fixed or portable computer system and that has a memory medium to be protected. The security and protection device (1) is located physically between the computer system (2) and the memory medium (MP) to be protected, in order to allow the computer system (2) access to the data and codes to be protected after execution of the protection functions independently of the machine code executed by the computer system (2) and requires no interaction with the processor of the system for the execution of these functions.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: January 7, 2014
    Assignee: Bull S.A.S
    Inventors: René Martin, Alain Filée
  • Patent number: 8432707
    Abstract: An AMB component and a connection interface for a memory installation with fully buffered Dimm memory modules connected in series. The AMB component is disposed on a connecting line from memory modules to a memory controller of the memory installation to re-amplify the connecting line between two consecutive FBD memory modules. The connection interface includes an AMB amplifier component for the connection of a main memory card that includes at least one processor, to an auxiliary memory card of the type having a series of memory modules. Two series of FBD memory modules are connected to respective FBD channels in the auxiliary memory card using FBD connectors in a daisy-chain arrangement.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: April 30, 2013
    Assignee: Bull S.A.S.
    Inventor: Jean-Jacques Pairault
  • Patent number: 8321687
    Abstract: A cryptographic system with a modular architecture. Memory modules make it possible to store information concerning authentication keys, data and commands, including a secure memory module for containing the keys with integrity checking and an emergency erase function. Various types of algorithm modules perform cryptographic functions of the cryptographic system by executing the commands stored in at least one memory module. External interface modules are utilized that make it possible to produce the link between the cryptographic system and external devices, through a standard or proprietary input/output bus. A control unit is responsible for the supervision of the various algorithm modules and the management of the keys, and a central interconnect module assures handling of secure exchanges between blocks.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: November 27, 2012
    Assignee: BULL S.A.S.
    Inventor: Patrick LeQuere
  • Patent number: 8103591
    Abstract: A method and system for flexible management of a plurality of activities executed within at least one computer hardware resource perimeter configured at least one multicellular computer platform. The activities are executed by identifying an activity using extended serial numbers attributed to the activity, authenticating the serial number of a subsystem on which execution of the activity is authorized, verifying the extended serial numbers, and recording the extended serial numbers as activity licenses.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: January 24, 2012
    Assignee: Bull S.A.S.
    Inventor: Alain Bouchet
  • Patent number: 8018736
    Abstract: The invention concerns the use of an AMB component (25) in a memory installation with fully buffered Dimm memory modules connected in series, characterised in that the AMB component (25) is placed on a connecting line (30) from the memory modules (2) to a memory controller (1) of the installation in order to re-amplify the connecting line (30) between two consecutive FBD memory modules (21, 22). The invention also concerns a connection interface that includes such an AMB amplifier component (25) for the connection of a maincard (3) that includes at least one processor, to an auxiliary memory card of the type with a series of memory modules (2), where the maincard has at least one pair of channels connected to the processor. Two series of FBD memory modules (2) are connected to respective FBD channels in the auxiliary memory card using FBD connectors (200) in a daisy-chain arrangement.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: September 13, 2011
    Assignee: Bull S.A.S.
    Inventor: Jean-Jacques Pairault
  • Patent number: 7966594
    Abstract: The invention relates to an automated method for inserting dummy surfaces (95) into the various layers of the physical design (121) of multilayer integrated circuits organized in interconnected units (2) containing interconnected blocks (30) composed of interconnected cells (3), implemented by an integrated circuit design system (100). The multilayer integrated circuit design (121), stored in the design system (100) is implemented layer by layer, through selective insertion of patterns of dummy surfaces (95), the selective insertion is based on an insertion hierarchy that respects the hierarchy of the physical design (121) of the integrated circuits, by means of individual implementation of the interconnected blocks (30) and first interconnection routing (31) for said interconnected blocks (30) and individual implementation of the interconnected units (2) and second interconnection routing (22) for said interconnected units (2).
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: June 21, 2011
    Assignee: Bull S.A.
    Inventors: Marta Zorrilla, Vivian Blanchard
  • Patent number: 7941771
    Abstract: A method for on demand functional verification of a software model of an application specific integrated circuit (ASIC), in a low-level programming language, which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model in order to create a verification platform. In a transmission mode, an autonomous circuit emulator is created by replacing the model in a low level programming language physically describing the circuit to be validated with a high level description generating response data in accordance with the functional specification of the design as a function of stimuli received. A verification mode includes integration of the software model in low level language of the circuit resulting from the design into a verification platform, and creation of a connection of a previously validated autonomous circuit emulator to the interfaces of the software model.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: May 10, 2011
    Assignee: Bull S.A.
    Inventors: Anne Kaszynski, Jacques Abily
  • Patent number: 7873662
    Abstract: In order to have operations of a central system executed by a satellite system, a linking structure is located between the central system and the satellite system. The linking structure includes: a communications link between the central system and satellite system; a control card, in the central system, that places said operations in one or more data blocks; and a coupler, in the satellite system, that sends through the link to the control card at least one read command to which the control card responds by sending said data block or blocks through the link to the coupler.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: January 18, 2011
    Assignee: Bull, S.A.
    Inventors: Denis Pinson, Patrick Sala, Jean-Paul Pigache
  • Patent number: 7873790
    Abstract: The present invention concerns a storage method and system (1) comprising processing means (11) and storage resources (20, 100) containing firstly storage means (20) including at least one physical library (P201 to P20n) and secondly memory means (100) called a cache (100), in which the processing means (11) of the storage system (1), vis-à-vis the computer platforms (101 to 10n), emulate at least one virtual library (V201 to V20n) from at least one physical library (P201 to P20n) which the storage system has under its control, characterized in that the processing means (11) of the storage system (1) comprise a management module (30) responsible for emulation and managing priorities over time for accesses to the storage resources (20, 100) using the results of calculations of at least one cache activity index per determined periods of time, and of at least one cache occupancy rate at a given time.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: January 18, 2011
    Assignee: Bull S.A.S.
    Inventors: Jean-Louis Bouchou, Christian Dejon
  • Patent number: 7865344
    Abstract: A method for creating a global simulation model of an architecture for models of integrated circuits under development, including reading an architecture description file of the global model and storing information related to all of the possible configurations instantiating the components and storing the corresponding information, topologically connecting the interface signals, physically connecting the interface signals, at the level of each instance of the components using a component and connection rule table, and storing the corresponding information, and automatically generating the HDL-type and HLL-type source files of the global simulation model.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: January 4, 2011
    Assignee: Bull S.A.
    Inventor: Andrzej Wozniak
  • Patent number: 7779112
    Abstract: A method and device for deploying a distributed monitoring of a computer system having a plurality of resources forming at least one monitored domain. The method includes specifying for each indicator to be deployed, the domain or domains of the computer system in which each indicator should be deployed and deploying the specified configuration using a configuration deployment agent that creates, for each resource to be monitored, a configuration agent to handle the creation of the indicators.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: August 17, 2010
    Assignee: Bull S.A.
    Inventors: Marc Herrmann, Xiaobo Li
  • Patent number: 7699180
    Abstract: A layout for packaging a computer rack comprises a transport pallet (2) and a computer rack; the computer rack being associable with casters extending vertically by a first distance relatively to a lower face of the rack. The computer rack is made integral with the pallet by two anchoring means distributed on the underside of the rack on either side of a vertical median plane (P1); the pallet includes two side modules and an intermediate supporting means separable from the remainder of the pallet and allowing the side modules to be connected. The side modules are removably attached to the anchoring means, so as to ensure that the computer rack is maintained in a horizontal position, and that the pallet is spaced away from the underside of the rack by a second distance (H2) smaller than said first distance.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: April 20, 2010
    Assignee: Bull S.A.S.
    Inventors: Emmanuel Mollard, Lionel Coutancier
  • Patent number: 7627813
    Abstract: This invention relates to a process for recognition and referencing of dynamic objects (22) in Internet pages (2) viewed by browsers (30) executed by users' computers (3), characterised in that it consists of a script (20) included in the Internet pages (2) containing dynamic elements (21) to be interpreted by all types of browsers (30) and to implement a step to test the type of browser (30) used to view the Internet page (2), so as to determine whether or not the following steps defined in the script (20) need to be implemented: automated routing (4) of Internet pages (2) and identification of dynamic elements (21); creation (5) of access references (25) to dynamic objects (22) corresponding to identified elements (21); instantiation (6) of dynamic objects (22) referenced within Internet pages (2) viewed by browsers (30).
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: December 1, 2009
    Assignee: Bull, S.A.
    Inventor: Genevieve Roser
  • Patent number: 7587714
    Abstract: The invention concerns the parameterization of a piece of software comprising parameters to be entered in order for the software to be used. The principle consists of subdividing the set of parameters into subsets, and of simultaneously displaying the subsets (SS1, SS2, SS3), the content of at least one selected subset, and the position within the set of each subset selected.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: September 8, 2009
    Assignee: Bull S.A.
    Inventor: Pascal Robilliard
  • Patent number: 7574696
    Abstract: A test monitor for a multiprocessor machine including a plurality of processors each configured to execute a test by interpreting a script language for writing tests, in which one of the processors executes a kernel part comprising instructions for conducting and monitoring the executed tests according to the scripts, and an application program interface provided using a library of functions for interfacing with firmware of the multiprocessor machine. The test monitor includes a method for executing instruction sequences simultaneously in several processors of a multiprocessor machine.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: August 11, 2009
    Assignee: Bull S.A.
    Inventors: Claude Brassac, Alain Vigor
  • Patent number: 7519831
    Abstract: The present invention concerns a cryptographic system (1) with a modular architecture. Memory modules (3, 3?, 3?) make it possible to store information concerning authentication keys, data and commands, including a secure memory module (3?) for containing the keys with integrity checking and an emergency erase function. Various types of algorithm modules (5, 5?, 5?) perform cryptographic functions of the cryptographic system by executing the commands stored in at least one memory module (3, 3?, 3?). External interface modules (4, 4?, 4?) are utilized that make it possible to produce the link between the cryptographic system (1) and external devices, through a standard or proprietary input/output bus. A control unit (6) is responsible for the supervision of the various algorithm modules and the management of the keys, and a central interconnect module (2) assures handling of secure exchanges between blocks.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: April 14, 2009
    Assignee: Bull S.A.
    Inventor: Patrick LeQuere
  • Patent number: RE41705
    Abstract: The present invention relates to a process and a device for handling the execution of a job in an open data processing system as a function of the resources. The process comprises the steps of: determining system resources available in virtual memory, real memory, temporary file space, and central processing unit utilization time during a given interval; computing the amount of resources preallocated to other requests and not yet used; comparing the amount of resources required for the execution of a job for which the request has been presented to the current amount of resources available minus the total amount of resources preallocated to other requests, in order to determine as a function of the result of this comparison the start, the deference or the denial of the start of the job requested The present invention relates to a process and a device for handling the execution of a job in an open data processing system as a function of the resources.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: September 14, 2010
    Assignee: Bull S.A.
    Inventors: Daniel Lucien Durand, Gerard Sitbon, Francois Urbain