Abstract: A coherence controller is included in a module which includes a plurality of multiprocessor units, each of which contains a main memory and processors equipped with respective cache memories. The module may be one of a plurality of similarly constructed modules connected by a router or other type of switching device. The coherence controller in each module includes a cache filter directory having a first filter directory for guaranteeing coherence between the local main memory and the cache memory in each of the processors of the module, and an external port connected to at least one of the other modules. The cache filter directory also includes a complementary filter directory, which tracks locations of lines or blocks of the local main memory copied from the module into other modules, and for guaranteeing coherence between the local main memory and the cache in each of the processors of the module and the other modules.

Abstract: The present invention relates to a modular interconnection architecture for an expandable multiprocessor machine. It comprises a first interconnection level (MI) comprising connection agents (NCSi) that connect the multiprocessor modules and handle the transactions between the multiprocessor modules, and a second interconnection level (SI) comprising external connection nodes (NCEj) that connect the nodes (Nj) to one another and handle the transactions between the nodes (Nj). Each external connection node (NCEj) comprises two connection agents identical to the connection agent (NCSi), connected head-to-tail, one of the two agents (NCS?j) receives and filters the transactions sent by the node (Nj) to which it is connected. The other agent (NCS?j) receives and filters the transactions sent by the other nodes (Nj) to which it is connected. Its applications specifically include the construction of an entire range of machines: UMA, QUASI-UMA, NUMA, cluster, etc.

Abstract: The invention relates to a process for assigning tasks in a multiprocessor digital data processing system having a preemptive operating system, and an architecture for implementing the process. The system comprises processors (200–203, 210–213) capable of processing the tasks in parallel, divided into groups (200–201, 202–203). An elementary queue (5a, 5b) is associated with each of the processor groups (200–201, 202–203) and stores tasks to be executed. All the tasks to be executed (T1 through T10) are stored in a table (4). Each of the tasks (T1 through T10) of the table (4) is associated with one of the queues (5a, 5b) and each of the tasks stored in the queues (5a, 5b) is associated with one of the processors (200 through 201). The associations are made by sets of cross pointers (p200 through p203, pp5a, pp5b, pT1, pT5, pT10, p5a1 through p5a4, and p5b1 through p5b10).

Abstract: The method of management of the hot insertion of an electronic card (11) in a system (10) comprises the successive connection of the card to two supply potentials (U0, Ui) available in a connector (20) so as to obtain transient connection signals (41, 42) during the hot insertion of the card, the detection of the transient signals for providing a binary signal (Vi), one binary state (Vi=1) of which represents the hot insertion of the card, and the use of said state of the binary signal (Vi) for rendering the card operational in the system. The hot insertion detector (37) includes a bistable logic circuit fed during the connection of the card to said potentials and provided with biasing means adjustable depending on the presence or otherwise of the transient signals.

Abstract: A method and a system for saving the local clock of a data processing area of a multicellular platform, configured from a management tool as a data processing server on a partitionable machine. For the management tool and each data processing area, an absolute reference clock is established. For each area comprising a local clock managing an operating activity, there is calculated and stored a backup attribute containing at least one time shift parameter of the parameters for management of the local time with respect to the absolute reference clock. For the subsequent execution of the operating activity on a successive different data processing area, parameters for management of the time of this activity with respect to the absolute reference clock are recalculated. The successive local clock, associated with the successive different data processing area is updated, prior to the launching of the operating activity to continue execution.

Abstract: The present invention relates to a process for remote authentication of a user (7) for local access to a local machine (4) of a network (5) having a server (3) managed by an administrator (8). The local machine (4) creates a challenge (D) which is communicated to the administrator (8), together with elements known by the user via communication means (9) independent from the network (5). A predetermined calculation is performed by means of the server (3) in order to obtain a first response (RD) to the challenge (D). The response (RD) is first transmitted to the user (7) obtained through the communication means (9). A calculation is performed by means of the local machine (4) in the same way as the server (3) in order to obtain a second response (RD1) to the challenge (D). The first and second responses (RD) and (RD1) and the local connection are authorized based on the result.

Abstract: For a set (Lk) of embedded systems, an authorized operator with identifier (OPj) creates a mother public key (KpM) and a mother private key (KsM). The identifier (OPj), the range of identifiers referenced (Lk) and the mother public key (KpM) are published. For each embedded system (SNi), a diversified key (KsMi) is created from the identifier (SNi) and stored. For every public key (Kp) generated by an embedded system, a cryptographic control value (Sci) is calculated on the public key (Kp), an algorithm identifier (CA1) and the utilization parameters (U) of this key, using a zero knowledge signature algorithm, and a certification request message (MRCA) that includes control value (Sci), the identifier of the operator (Opj), and identifier (SNi) is transmitted to a certification authority, which retrieves the identifier (Opj) and the value of the mother public key (KpM).

Abstract: The invention relates to data warehousing systems (1) wherein a search engine (2) implemented by a decision application server (4) acts on a relational database (6) that contains a set of target records. The engine (2) is activated by queries for selecting records based on given criteria and comprises a module (8) for preconditioning the database (6) supplying a preconditioned encoded table (10), periodically updated at the same time as the relational database (6) itself, to a machine with vectorial capabilities (9) in order for it to be processed. It also comprises an agent (7) for extracting target records, activated by the queries based on the result of the processing of the table (10) installed in the machine with vectorial capabilities (9), from the relational database (6).

Abstract: The present invention concerns a cryptographic system (1) with a modular architecture. Memory modules (3, 3?, 3?) make it possible to store information concerning authentication keys, data and commands, including a secure memory module (3?) for containing the keys with integrity checking and an emergency erase function. Various types of algorithm modules (5, 5?, 5?) perform cryptographic functions of the cryptographic system by executing the commands stored in at least one memory module (3, 3?, 3?). External interface modules (4, 4?, 4?) are utilized that make it possible to produce the link between the cryptographic system (1) and external devices, through a standard or proprietary input/output bus. A control unit (6) is responsible for the supervision of the various algorithm modules and the management of the keys, and a central interconnect module (2) assures handling of secure exchanges between blocks.

Abstract: A test monitor loaded into a multiprocessor machine comprises a program (31) designed to interpret a script language for writing tests, a program (29) that constitutes a kernel part for conducting the tests according to the scripts, and a library (30) of functions that constitutes an application program interface with the firmware of the machine 1. This monitor implements a method for executing instruction sequences simultaneously in several processors (3, 4, 5) of a multiprocessor machine (1). The method comprises a first step (8) in which a single processor operating system is booted in a first processor (2) and a second step (9) in which the first processor (1) orders at least one other processor (3) of the machine, called an application processor, to execute one or more instruction sequences (17, 18, 19) under the control of said first processor.

Abstract: A method of transferring data in a processing system comprising a shared memory for storing data blocks, a plurality of processors, at least one of the processors having a cache memory for the data blocks, a plurality of data buses to each one at least one processor is connected, cross-bar for selectively connecting the data buses and the shared memory therebetween; the method comprises the steps of requesting the reading of a data block from the shared memory by a requesting processor, if the requested data block is present in modified form in the cache memory of an intervening processor, requesting an access to the corresponding data bus by the intervening processor, granting the access to the intervening processor, and to any other data bus available to the cross-bar, and sending the modified data block onto the data bus corresponding to the intervening processor and then onto the other data buses available.

Abstract: The present invention relates to a method for calculating an indicator of a network management system comprising at least one submanager that monitors a part of the network. The submanager comprises a plurality of modules that allow communication with the equipment units of the network and with a main manager., At least one equation defining an indicator and evaluated by an indicator module of the submanager comprises at least one object attribute, at least one index whereof is variable. The method comprises a step for the reception by the indicator module of a notification transmitted by a model configuration module, which notification comprises an address of an equipment unit and an identification of an equation representing an indicator.

Abstract: A method of managing a personal event log specific to an operating activity exocuted on a multiple-cell computer platform comprises a step of recording the event in a common event log together with an identifier of the acrivity that is saving the event while an activity is saving an event; and prior to an activity consulting its personal event log, a step of reconstructing the personal event log from the common event log, said reconstruction step including an operation of selecting from the common event log only those events which are associated with the identifier of the activity in order to include those events in the personal event log reconstructed for said activity.

Abstract: A method for automatic updating of an access path to the system disk of a hardware perimeter of computer resources during launching of an operating activity on this perimeter includes during the installation of a new system disk, a step of saving the lower part of the access path to the new system disk in a list of access paths, on the occasion of the definition of the operating activity, a step of associating with this activity one of the lower parts stored in the list of access paths, and on the occasion of the launching of the activity on a perimeter, a step of automatic updating of the access path contained in the working memory of the perimeter as a function of the lower part of the access path associated with this activity during its definition. A system and memory for implementing the method are also discussed.

Abstract: The invention relates to a process for dynamically reconfiguring an information processing system (1), particularly a so-called “SMP” symmetric multiprocessor system. The process comprises a preliminary step for detecting a failure risk of one of the components of the system (CPU3). Following this detection, the system (1) is placed in a coherent, so-called “frozen” state in a first step with the aid of programs (J1-J4) executing specific tasks. A second step consists of reconfiguring the system by reallocating/de-allocating all or some of the components (CPU1-CPU4). In a third step, the component (CPU3) that presents a failure risk is isolated. The pending interruptions (4) are processed and the current tasks (6) are executed prior to the “freeze.” Likewise, the queues of tasks to be executed are purged prior to the “freeze.” Then, the subsequent tasks and interrupts are inhibited until a final step that consists of releasing the system (1).

Abstract: The present invention relates to a method and a system for generating a global simulation model of an architecture.

Abstract: The present invention concerns a method for the functional verification of a software model (40) of an integrated circuit on demand (ASIC), in a low-level language (for example of the HDL type), which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model of the circuit in order to create a verification platform, comprising the following two steps:

Abstract: A router comprising a number n of inputs (9, 19, 29, 39) and a number n of outputs (49, 59, 69, 79) is intended for routing data packets from the inputs (9, 19, S29, 39) to the outputs (49, 59, 69, 79). The router includes a reticular routing switch constituted by a number n of first incoming lines (5, 6, 7, 8), a number n of second incoming lines (1, 2, 3, 4), a number n of first outgoing lines (50, 60, 70, 80) and a number n of second outgoing lines (10, 20, 30, 40, each of the first incoming lines (5, 6, 7, 8) being respectively connected to an input (9, 19, 29, 39) and each of the first outgoing lines (50, 60, 70, 80) being respectively connected to an input (49, 59, 69, 79).

Abstract: The present invention relates to a method for managing the persistence of EJB components (8) integrated into an EJB server (3) of a computer system (1), consisting of managing the persistence through an LDAP directory (4) by: deploying EJB components that integrate information into the LDAP entries of the directory (4); exchanging information between a client (2) and the LDAP directory (4) while performing a conversion using conversion classes (25) in order to perform operations required by the client (2); The present invention also relates to the system for implementing said method.

Abstract: A device for at least two electronic components disposed opposite each other and on each side of the same connection board by application of pressure. At least one small clamping column is arranged to be slid into an opening provided in the connection board, and to receive, at each of its ends, a spring which causes a resilient bracing force to be exerted on a bearing plate in the direction of the connection board. Clamping abutments serve to clamp the clamping column to the connection board. Each clamping column is disposed on each side of the connection board, and spaced from each other by a distance strictly greater than the thickness of the board so as to provide between the board and the abutments a clearance for balancing the retaining force between the two bearing plates.