Abstract: A computer system having physical resources including a plurality of processors (10, 11, 12 ,13, 20, 21, 22, 23) and a physical memory (14, 24) for executing processes in a virtual address space by means of a virtual storage manager (59) that maps real pages of physical memory with virtual pages of the virtual address space. A scheduler (55) is arranged for scheduling the execution of threads of processes in the processors. The computer system includes at least one named set of physical resources RS (50, 51, 52) including a given number of identified processors (10, 11, 12, 13) and a given number of identified real pages (18, 19, 36). The scheduler (55) is configured to have a thread of an identified process executed by one or more of the processors of the set RS and the virtual storage manager (61) maps a real page of the set RS to a virtual page if the thread causes a page fault.

Abstract: The subject of the present invention is a device (1) for mounting at least two electrical components (4A, 4B) on a printed circuit card (2), the card (2) comprising connection pads on both of its sides. According to the invention, the card (2) is traversed by holes (11-14) for receiving mounting means that extend through the printed circuit card in order to mount the electrical components (4A, 4B) on opposite sides of the card. Another subject of the invention is the tool (35) for mounting or removing an electrical component mounted on a printed circuit card as mentioned above. This tool comprises means for exerting pressure on a first electrical component (4A) attached to a first side of the printed circuit card, in order to mount or remove a second electrical component (4B) on the opposite side of the printed circuit card (2).

Abstract: The present invention concerns a method for exchanging information between processes, tasks or computer applications executed by different operating systems coexisting on the same computer or the same hardware platform.

Abstract: A high-speed random number generator (1) comprising a physical random number generator, having a data input, an output and a pseudo-random generator coupled to the output of the physical random generator. The pseudo-random generator has an input adapted to receive a germ delivered by the physical generator and deliver at an output a pseudo-random output signal. The physical generator comprises a logic circuit that includes at least a data input (D) and a clock input (CLK), the data input (D) receiving a first “high frequency” clock signal H1 and the clock input (CLK) receiving a second “low frequency” clock signal H2, with the “high frequency” signal H1 being sampled by the “low frequency” signal H2. The two clock signals H1 and H2 are of different frequencies respectively and issue from two different first (OSC1 and OSC2) operating asynchronously from one another and not adhering to the setup time of the logic circuit (10).

Abstract: A process, a tool and a computer for analyzing and locating hardware failures in a computing machine storing information on operational errors generated by the various sensible hardware components of the machine, characterized in that it consists of creating a man/machine interface (I) through which the components and the rules for interpreting errors are described in a structural language and used by the machine as external parameters in correlation with the error information to detect the malfunctioning component or components. The preventive process is particularly adopted for computer hardware maintenance.

Abstract: The invention concerns a method for the automatic recognition of simulation configurations of integrated circuits under design comprising at least two components connected to one another directly or indirectly, for the functional verification of the circuits through simulation tests, characterized in that it comprises:

Abstract: The subject of the present invention is a device (1) for mounting at least two electrical components (4A, 4B) on a printed circuit card (2), the card (2) comprising connection pads on both of its sides. According to the invention, the card (2) is traversed by holes (11-14) for receiving mounting means that extend through the printed circuit card in order to mount the electrical components (4A, 4B) on opposite sides of the card. Another subject of the invention is the tool (35) for mounting or removing an electrical component mounted on a printed circuit card as mentioned above. This tool comprises means for exerting pressure on a first electrical component (4A) attached to a first side of the printed circuit card, in order to mount or remove a second electrical component (4B) on the opposite side of the printed circuit card (2).

Abstract: The invention relates to a search engine (2) implemented by a decision application server (1) acting on a relational database (6) that contains a set of target records. The engine (2) is activated by queries for selecting records based on given criteria and comprises means (8) for preconditioning the database (6) supplying a preconditioned encoded table (10), periodically updated at the same time as the relational database (6) itself, to a machine with vectorial capabilities (9) in order for it to be processed. It also comprises means (7) for extracting target records, activated by the queries based on the result of the processing of the table (10) installed in the machine with vectorial capabilities (9), from the relational database (6).

Abstract: The method comprises at least one cycle comprising the following steps: creating a request (87) designating a target object (81) to be accessed in the tree (80) representing system resources and having a scope of only one level below the target object, using an access protocol attribute of the target object (81) indicating its access protocol (Pc) to allow access to the target object, and obtaining via the request a response that includes at least the naming attribute of each object (82, 83) contained in the scope of the request, and if at least one object contained in the scope of the request has an access protocol different from that of the target object, the access protocol attribute of this object.

Abstract: The subject of the present invention is a process for optimizing the flow of data between at least one client application and at least one request management system that includes at least one object having states and values capable of being modified wherein the client application sends at least two successive requests for interrogating states or values of objects included in a management system. Communication between the client application and the management system takes place through a communication system. The process is characterized in that on initialization, the management system transmits to the client application, at the request of the client application, a set of objects that includes all or some of the objects included in the management system. In response to an interrogation request from the client application, the management system transmits to the client application any modifications that include the states and/or values of at least one object of this set that have been modified.

Abstract: A method and a device is disclosed for encoding/decoding digital data transmitted through a serial link, particularly of the so-called “8B/10B” type. A full encoded binary word includes 8 data bits and a 2-bit label. The logical state of a center bit triplet of the byte is detected. When all of the bits are in the same logical state, the center bit of the triplet is inverted prior to transmission. Otherwise, the byte is transmitted as is. The label is forced to the logical configuration “10” when there is a bit inversion, and to “01” in the opposite case. Upon decoding, this configuration is tested and the center bit received is selectively inverted as a function of the result of the test. In a preferred variant, the method also includes tests of the label and the triplet after decoding, when there has been a bit inversion in the encoding.

Abstract: An edge multiplier circuit comprises a chain of N phase-looped delay cells (130, 131, 132, 133, 134). An order of cells to be delayed is determined by action loops. A first action loop (116, . . . , 128) is utilized for values of j varying from 1 to N, each corresponding to a total delay equal to j times an elementary delay (Te) of a cell. The delay is applied to the chain of N delay cells. An action of the first loop comprises a second action loop (118, . . . , 127) for values of i varying from 1 to N, each corresponding to a rank of a cell in said chain. An action of the second loop calculates a delay error (a (j, i)) output from the cell of rank i relative to an ideal delay that distributes the total delay of the chain equally to each cell.

Abstract: A method and a system for saving the local clock of a data processing area of a multicellular platform, configured from a management tool as a data processing server on a partitionable machine.

Abstract: An interconnection interface for transmitting digital data between a sending module and a receiving module connected to one another through point-to-point serial links, forming a global data link. Each of the modules are provided, firstly, with a multiplexing unit associated with each of the serial links disposed in the module's physical layer, so as to distribute data transmitted through the global link at a speed determined by the sending module to a given number of parallel links, with each of these parallel links conveying a part of the transmitted data at a speed higher than the sending module data speed; and secondly, with a demultiplexing unit associated to the parallel links conveying received data parts, so as to synchronously and integrally reconstitute these received data parts at a speed accepted by the receiving module.

Abstract: The method of management of the hot insertion of an electronic card (11) in a system (10) comprises the successive connection of the card to two supply potentials (U0, U1) available in a connector (20) so as to obtain transient connection signals (41, 42) during the hot insertion of the card, the detection of the transient signals for providing a binary signal (V1), one binary state (V1=1) of which represents the hot insertion of the card, and the use of said state of the binary signal (V1) for rendering the card operational in the system. The hot insertion detector (37) includes a bistable logic circuit fed during the connection of the card to said potentials and provided with biasing means adjustable depending on the presence or otherwise of the transient signals.

Abstract: In a computer platform (PF) comprising at least one unit (M1, M2), each including at least one respective processor (PRO1-PRO2, PRO3-PRO5) and at least one respective interrupt controller (CI1, CI2), and an operating system (SE) including a basic kernel (NOY) for creating extension modules external to said basic kernel, at least one interrupt managing extension module (MEX1, MEX2) external to the basic kernel (NOY) is created in order to relieve the basic kernel of the management of interruptions.

Abstract: A power distribution unit (PDU) for supplying power to at least one electrical device (APP1-APP12), comprises at least one distribution point (P) for the power supply, and at least one female outlet (J1-J12) on its accessible side. The outlet is adapted to receive a male connector of a cable of an electrical device (APP1-APP12). The point (P) is electrically connected by a respective electrical cable to at least one manually resettable circuit breaker (BRK1-BKR6). The at least one circuit breaker comprises a respective push button (POU1-POU6) for resetting the circuit breaker. The circuit breaker (BRK1-BRK6) is connected by a respective electrical cable to the at least one female outlet (J1-J12). The circuit breaker (BRK1-BRK6) is located inside the unit and at least one reset mechanism capable of resetting the at least one circuit breaker is provided. Several circuit breakers may be supported in line and the reset mechanism is capable of resetting all of the circuit breakers simultaneously.

Abstract: A process and interface for interconnection of multiprocessor modules by point-to-point serial-to-parallel links. Data processing or data communication modules (A and B) are interconnected by means of high-speed point-to-point serial links conveying multiplexed information organized into frames comprising a start-of-frame recognition pattern. The process, on transmission and on reception, performs an analog synchronization of the basic clocks of the modules to a reference clock generated by one of the modules designated as a reference module, called the master module, the other modules being called slave modules, and a digital synchronization of the start-of-frame of each slave module to the start-of-frame sent by the master module.

Abstract: The present invention relates to a key recovery process used for strong encryption of a message sent by an entity, which message is either to be stored locally or transmitted to another entity, the reading of a message requiring a decryption key which can be reconstructed at least by a trusted third party for key recovery, while added to the message are a compensation field and a compulsory control field which itself comprises at least one key recovery field for allowing at least one trusted third party to supply the decryption keys that enable the encrypted message to be read. This key recovery process is remarkable in that the compulsory control field also comprises, in unencrypted form, the current date as well as the agreement number of the encryption hardware/software and, encrypted under a daily intermediate key, the dialogue key.

Abstract: A variable frequency ring oscillator is controlled by a control signal and has an odd number of cascaded inverting gates. The inverting gates each have input terminals receiving an input signal. Except for the first of the cascaded inverting gates, each input signal on a gate is the output from the preceding inverting gate. The input terminal of the first of the inverting gates receives the output of the last of the inverting gates. At least one inverting gate is a cell having a gain variable as a function of a control signal. An output signal ext of the circuit is an inversion of an input signal inp and has a hysteresis that is a function of a control signal cont. The term “hysteresis” as used herein signifies, for example, a variable frequency signal remaining substantially in its current state for a certain length of time after which the variable frequency signal changes state with a magnitude that is a function of a control signal, upon change of state of an input signal.