Abstract: The invention relates to a process for optimizing accesses to a database. This process allows client applications to request a CMIS-DB server, via an online configuration, to customize the generic representation for the object classes for which the access times must be optimized in order to reduce the search times for the object instances selected, by performing a step for configuring the physical storage of an object class to be optimized, which consists in the creation of an object instance of the storage definition class (mocStorageDefinition), in which are declared the attribute or attributes of the class to be optimized, which will be indexed when physically stored on a disk.

Abstract: A disk cache device for secure writing comprising a backup power supply source (62) for supplying backup power for a given duration to a computer system fed by two main electric power supply devices (60, 61) and comprising at least one hard disk drive (1a, 1b, 1c), and a host system (3). All of the disk drives (1a, 1b, 1c) are linked by a bus (2) to a connection (30) of the host system (3) (host bus adapter), and a monitor (50) for monitoring at least the backup electric power supply source (62) and the main power supply devices (60, 61). Monitors (50) are connected to the interface (2) and can be interrogated by an interrogator (31) for interrogating the host system (3) so that the latter can enable the write disk cache function, or not, in the write commands to be sent to the disk drives (1a, 1b, 1c) in accordance with the information gathered by the monitoring means (50).

Abstract: The invention relates to a communication process via an internet network that comprises distributed systems (S1). Each system (S1) is connected to the network (SRX) via a standard interface module (10), standard software layers (12, 13) comprising a stack of addresses and protocols, and hosts software entities (SVA, SVB). The latter and the systems (S1) are provided with a network address in a virtual subnetwork to which the system itself (S1) and said software entities (SVA, SVB) are connected via a specific interface module (11, 20, 30) and specific software layers (21-22, 31-32) comprising a stack of addresses and protocols. The addresses and names of the systems (S1) and of the software entities (SVA, SVB) connected to the virtual networks (SVNy) are stored in a domain name directory (DNS1), making it possible to directly address one of the software entities (SVA, SVB).

Abstract: The lock architecture for a computer system comprises several processors (10, 11, 12, 13) such that each processor (10) requesting a resource of the system takes control of said resource if a first lock state indicates that said resource is free. The requesting processor is placed on active standby if a second lock state indicates that said resource is busy. A lock includes a first and second lock state. The first lock state corresponds to a null value, and the second lock state corresponds to a non-null value.

Abstract: In a computer system with a virtual addressing mechanism, a process for the de-allocation of physical pages sets, by means of a first pointer (ptr) on a line (5) of a conversion table (1) that contains an indicator (Ref) that has been set to a first state (“referenced”) by a processor (2), the indicator (Ref) to a second state (“non-referenced”) if the state is (“referenced”) and de-allocates the line (5) if the state is (“non-referenced”). The de-allocation process claimed by the invention sets an indicator (ref) which has been set to the first state (“referenced”) by the processor (2) on a line (13) of the conversion table (1) to a second state (“non-referenced”) if the state is (“referenced”) by means of a second pointer (ptr+&Dgr;) on the line (13) upon the indication of an attribute value (Co) for said line (13). The de-allocation process can therefore be used for a cache mechanism.

Abstract: The present invention relates to a process for transforming and routing data between agent servers present in some machines and a central agent server present in another machine. The agent server comprises autonomous agents (5) that communicate via notifications, a storage layer and an agent machine comprising an execution engine, a communication channel and two message queues for the notifications, a local queue (mqIn) and an external queue (mqOut). The execution engine takes a notification in the local queue, determines and loads the corresponding agent for each notification, has the agent react to the notification, which agent can then change its status and/or send notifications to the communication channel (2), which stores them in the local queue if they are addressed to a local agent and in the external queue if they are addressed to an agent of another server.

Abstract: On a machine with non-uniform memory access distributed over several modules, each module includes one or more processors for executing tasks on a virtual or physical addressing space by effective addresses generating logical page numbers to which it is possible to make physical page numbers correspond in the memory by a correlation tale. The generation of a logical page number causes a first-level page-fault type exception when the logical page number is absent from the correlation table. The method includes a step for activating a function (Trace), following each first-level page-fault type exception, a trace function, which records the value of the effective address that has generated the logical page number that has caused the exception, the date when the exception is caused, an identifier of the task using the effective address, an identifier of the processor executing the task and the physical page number corresponding to the logical page number that has caused the exception.

Abstract: The present invention relates to a bidirectional two-way CMOS link of the type including a tailored transmission line (AB) connecting two integrated circuits to its two ends. The integrated circuits respectively including a transceiver that includes a transmitter stage (7; 20) and a receiver stage (10), interfacing with the transmission line (AB) and controlled to transmit or receive digital data exchanged over the transmission line (AB) as a function of a control signal (transmission_gd) to put it in either the transmission mode or the reception mode, the transceivers never being in the same mode at the same time. The link is characterized in that each transceiver includes at least one PMOS transistor (MA), and one (NMOS) transistor (MB), which are controlled respectively by the control signal and are dimensioned and arranged to adapt the link to the two ends of the transmission line (AB). The invention in particular is utilized in tailoring of links that connect processors of a multiprocessor platform.

Abstract: Process for interconnecting between data processing or data communication modules (A and B) by means of high-speed point-to-point serial links conveying multiplexed information organized into frames comprising a start-of-frame recognition pattern. It consists, on transmission and on reception, of performing an analog synchronization of the basic clocks of the modules to a reference clock generated by one of the modules designated as a reference module, called the master module, the other modules being called slave modules, and of digitally synchronizing the start-of-frame of each slave module to the start-of-frame sent by the master module.

Abstract: The invention concerns a method and a device for encoding/decoding digital data transmitted through a serial link (Is), particularly of the so-called “8B/10B” type. The full encoded binary word includes 8 data bits (A . . . H) and a 2-bit label (X1X2). The logical state of a center bit triplet (CDE) of the byte is detected. When all of the bits are in the same logical state, “0”) or “1,” the center bit of the triplet (D) is inverted (4) prior to transmission. Otherwise, the byte is transmitted as is. The label (X1,X2) is forced (7) to the logical configuration “10 ” when there is a bit inversion, and to “01” in the opposite case. Upon decoding, this configuration is tested and the center bit received is selectively inverted as a function of the result of the test. In a preferred variant, the method also includes tests of the label and the triplet after decoding, when there has been a bit inversion in the encoding.

Abstract: The large-scale symmetric multiprocessor server with a multimodule architecture includes N identical multiprocessor modules 50, 51, 52, 53. The module 50 includes a plurality of multiprocessors 60, 61, 62, 63 equipped with a cache memory and at least one main memory connected to a coherence controller 64 that includes an external port 99 connected to at least one of the multiprocessor modules 51, 52, 53 outside the module 50 and a cache filter directory 84 SF/ED designed to guarantee coherence between the mass memory and the cache memories of the modules, the cache filter directory 84 including a local presence vector 86 that keeps track of the memory lines or blocks copied into the cache memories of the module 50 and an extension 88 that keeps track of the coordinates of the memory lines or blocks copied from the local module 50 to an external module 51, 52, 53.

Abstract: The invention relates to an architecture for management of vital data in a multi-module digital data processing machine (1) and the process for its implementation. Each module (M1 through Mn) comprises a physical nonvolatile memory (NVM1 through NVMn) in which vital data is stored. A first area (G1 through Gx) stores global vital data obtained by copying and associated with the operation of the machine (1). A second area (L1 through Lx) stores local vital data associated with the operation of the module (M1 through Mn). A virtual nonvolatile memory in two parts, global memory and local memory divided into windows, makes it possible, under the control of an extension of the operating system, to address the physical nonvolatile memories (NVM1 through NVMn). The windows of a defective module (M1 through Mn) are not visible. At the startup, a specific firmware determines the state of the modules (M1 through Mn).

Abstract: The present invention relates to a disk storage subsystem with multiple configurable interfaces, characterized in that it comprises at least one interface adapter board (1a, 1b), at least one drawer (4), each comprising a plurality of disks (20), each drawer (4) being connected to an adapter board (1a or 1b) by SCSI disk interfaces (2), a first adapter board (1a or 1b) comprising a switch (11) for modifying the addressing system of the disks (20) of at least one drawer (4), the adapter board or boards (1a, 1b) each comprising two independent single-ended/differential-ended SE/DE converters (7), each SE/DE converter (7) being connected to a drawer (4) and fed by either of two direct current/direct current DC/DC converters (7) of the adapter board (1), and two external SCSI connectors (10) being connected to each SE/DE converter (7).

Abstract: The present invention relates to a process and a system for network and system management. The process for network management comprises at least one submanager (COACH) located in a containing tree between a main manager (AD) and the equipment units of a local area network. The submanager is located in the local area network (RLE) and is managed by the main manager (AD). A subnetwork comprises various modules that communicate with one another and with the main manager (AD) through a kernel (N). The modules poll the equipment of the subnetwork and receive the alarms sent by agents (SNMP) operating in the equipment units of the subnetwork.

Abstract: A method of automated proving for unrestricted first-logic to test the satisfiability of clause sets describing an industrial system which applies the instance generation rule ( IG ) ⁢   ⁢ Ψ Ψ ⁢   ⁢ σ where &PSgr; is a term, &sgr; a substitution and &PSgr;&sgr; an instance of &PSgr; yielded by the substitution &sgr;, and is characterized in that, instance subtraction is defined as the substraction of the instance &PSgr;&sgr; from &PSgr; resulting in a generalized term which is a triplet <&PSgr;, &sgr;, &Lgr;> where &Lgr; is a finite set of standard substitutions {&lgr;1, . . . , &lgr;n} and defined by GE(<&PSgr;, &sgr;, &Lgr;>)=GE(&PSgr;&sgr;)−GE({&PSgr;&lgr;1, . . .

Abstract: A computer system comprises a nonuniform access memory distributed in several places of residence. The memory accesses a physical resource of the memory at a physical address constituted by a field of i bits and a field of j bits. The memory comprises a table with a number of rows equal to a power (i−j) of two, each row being accessible by a field of (i−k) bits of the physical address containing an identifier of the place of residence of the resource. The process for identifying a place of residence of a physical memory resource thereof consists of simply reading the identifier in the row of the table referenced by the field of (i−k) bits.

Abstract: The present invention concerns a package for an integrated circuit (3) of the type comprising a cavity (2) in which the integrated circuit (3) is mounted, the active surface (10) of the integrated circuit (3) being electrically connected to the package on the level of connection (Nc) of an array of balls (13i) to the package, providing a mechanical and electrical link between the integrated circuit (3) and a printed circuit card to which the package must be assembled. It is characterized in that it comprises an additional layer (14) that is rigid and electrically neutral, mounted on the level of connection (Nc) of the integrated circuit (3) and the balls (13i) and containing the balls (13i). It particularly applies to the connections of BGA and PBGA packages.

Abstract: A videoconferencing center (31, 33) for data communications and teleprocessing is provided which comprises first routing switches having a plurality of sending ports (51, 53, 55, 57) and a plurality of receiving ports (50, 52, 54, 56), each sending port adapted to be operatively connected to a receiving data terminal equipment unit (10, 28, 29) or to a receiving port of second routing switch (32, 34), each receiving port adapted to be operatively connected to a sending data terminal equipment unit (10, 28, 29) or to a sending port of another group switching center (32, 34). Each receiving port is assigned a receiving stack (102) that is addressable in a single logical address space and each sending port is assigned a sending stack (103) for containing addresses of said single logical address space. The single logical address reduces the risk of losing data received, which risk results from the necessary limits on physical addresses of stacks.

Abstract: The components of performance analysis considered within the scope of the invention are, in particular, the determination of the speed at which a circuit or a circuit component can generate output signals from input signals, and the noise immunity of the circuit. The process for evaluating the performance of a very high scale integrated circuit comprises: a first step (E1) in which, for each lead (Li) of said circuit, an equivalent coupling capacity value (CTi) relative a fixed potential, is generated as being a sum of the existing real coupling capacity values (Cij) of leads (Lj) of said circuit with said lead (Li), each of which is assigned a weighting coefficient (Kij); and a second step (E2) following said first step (E1), in which a switching time interval ([tid,tif]) in each lead (Li) is generated as being a function of said equivalent capacity (CTi). The fixed potential may be ground.

Abstract: A tool at the service of a distributed application running on machines of a distributed data processing system running in a local area network, intended for balancing the load on each of the machines of the system, includes a master daemon and a plurality of agent demons. The master and each of the agents calculate the load of the machine on which they are running. The master collects the load data of each of the agents at a first sampling interval and sends that collected load data to all of the agents. At the request of the distributed application, the local agent closest to the application indicates to the application which machine has the lightest load. The application then makes the decision to request the machine with the lightest load to execute the services the application requires. As necessary, the tool selects a master from the agents, thereby ensuring the existence and uniqueness of a master at all times, regardless of failure affecting one 1010 or more machines in the data processing system.