Patents Assigned to Cadence Design Systems, Inc.
  • Patent number: 10235482
    Abstract: A method for obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a logic path from an input to an output in the partition netlist is provided. The method includes identifying a first delay arc for the logic path including circuit components from the partition netlist, and configuring a first input stimulus vector to invert the input in the partition netlist and to induce a current through at least one of the plurality of circuit components. When a second input stimulus vector is associated with a second delay arc that is equivalent to the first delay arc in the logic path, the method includes selecting one of the first or second input stimulus vectors for a set of input stimuli vectors. The method further includes determining an electromigration effect on the partition netlist with the input stimuli vectors.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: March 19, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Aswin Ramakrishnan, Jalal Wehbeh, Robert MacDonald, Federico Politi, Ajish Thomas
  • Patent number: 10234504
    Abstract: According to certain aspects, the present embodiments relate to optimizing core wrappers in an integrated circuit to facilitate core-based testing of the integrated circuit. In some embodiments, an integrated circuit design flow is adjusted so as to increase the use of shared wrapper cells in inserted core wrappers, and to reduce the use of dedicated wrapper cells in such core wrappers, thereby improving timing and other integrated circuit design features. In these and other embodiments, the increased use of shared wrapper cells is performed even in the presence of shift registers in the integrated circuit design.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: March 19, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Subhasish Mukherjee, Jagjot Kaur, Vivek Chickermane, Susan Marie Genova
  • Patent number: 10237052
    Abstract: Systems and methods disclosed herein provide for effectively eliminating the rotational and static phase skews between the in-phase (I) and quadrature (Q) clocks generated by phase interpolators in decision feedback equalizer based receivers. Embodiments of the systems and methods provide for (i) a ring oscillator that eliminates the rotational phase skews and (ii) a plurality of clock mixers that eliminate the static phase skews.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: March 19, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Christopher George Moscone
  • Patent number: 10235490
    Abstract: Disclosed herein are embodiments of systems, methods, and products using a center access direction for pin figures during an abutment of instances in an integrated circuit (IC) design. Using a center access direction allows an electronic design automation (EDA) tool to overlap the centers of the pin figures to be merged. Once the centers of the pin figures are overlapped, the EDA tool runs one or more merging and optimization algorithms to abut the circuit devices containing the pin figures. The EDA tool therefore is computationally efficient and yet provides more functionality: unlike the conventional system, the EDA tool does not have to align the pin figures and calculate an offset to overlap the pin figures post alignment. Furthermore, the EDA tool can overlap the pin figures from any angle and is not confined to rectilinear access direction of the conventional systems.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: March 19, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Mallon, Gilles S. C. Lamant, Kenneth Ferguson, Monika Bijoy
  • Patent number: 10223495
    Abstract: The present embodiments relate generally to integrated circuit design, and more particularly to techniques for providing enhanced visual information about a shape of interest in a hierarchical design. For example, embodiments relate to automatically and dynamically creating or adjust a highlight set in a graphical user interface for providing hierarchical information about shapes in a hierarchical design in a more productive manner, and possibly concurrently with other textual information about shapes that is being displayed. In these and other embodiments, these automatic and/or dynamic highlight sets can be based on the relationship between a current cursor position and shapes of a hierarchical design that is currently being edited using a GUI of a layout editor tool that is adapted with the functionality of the present disclosure.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 5, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sunil Agrawal, Devendra Deshpande
  • Patent number: 10225115
    Abstract: A system and a method for detecting a low-frequency periodic signal (LFPS) include at least one comparator performing a threshold comparison on an analog input signal over a period of time. A sampling circuit generates digital signals by sampling an output of the at least one comparator. A digital detection circuit applies a set of detection rules to the digital signals. The detection rules are configured to detect a presence or an absence of an LFPS based on predefined criteria concerning characteristics of the digital signals.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: March 5, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Mathieu Gagnon, Santiago Luis Bortman, Eric Harris Naviasky, Guillaume Fortin, Julien Faucher
  • Patent number: 10222417
    Abstract: Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments relate to methodologies for utilizing these protection layers after manufacture of the integrated circuit and incorporating these protection layers in an integrated circuit design flow.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 5, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Akhil Garg, Dale Meehl, Sahil Jain
  • Patent number: 10223484
    Abstract: A system, method, and computer program product for facilitating model binning in circuit simulators. Embodiments enable specification of models spanning binning dimensions, such as device width and length, in a model group via inheritable model bins. New simulator modeling syntax and semantics eliminate much of the redundancy and parsing overhead from model parameter specifications in foundry process design kits. Indirect and optional inheritance is also enabled, allowing for fine grain and coarse grain grids in the same model group.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 5, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Donald J. O'Riordan, Richard J. O'Donovan, Saibal Saha, Jushan Xie
  • Patent number: 10216888
    Abstract: The present disclosure relates to a system and method for constraint validation in an electronic design. The method may include receiving an electronic design at an electronic design automation application and analyzing at least a portion of the electronic design at a constraint validation tool configured to analyze one or more physical constraints in a design layout associated with the electronic design. The method may further include applying one or more programmable electrical rule check (“PERC”) rules and one or more constraints to the electronic design, wherein the one or more PERC rules are configured to perform one or more electrical rule checks.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: February 26, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mikhail Kanshin, Andrey Freidlin, Alexey Kalinov, Andrei Savelev, Douglas M. Den Dulk, Wojciech Wojciak
  • Patent number: 10216887
    Abstract: Various embodiments implement an electronic design with power gate analyses using time varying resistors. Design data of an electronic design or a portion thereof may be identified at an electronic design implementation module. First stage electrical characteristics may be generated at least by performing a first stage electrical analysis on a reduced representation of the electronic design or the portion thereof. Second stage electrical characteristics may further be generated at least by performing a second stage electrical analysis on a parasitic injected representation of the electronic design or the portion thereof with a time-varying model for the power gate. The electronic design or the portion thereof may then be further implemented based in part or in whole upon the one or more electrical analyses or simulations.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 26, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: John Yanjiang Shu, Wei Michael Tian, Richard J. O'Donovan
  • Patent number: 10216880
    Abstract: Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a load-balancing process. In another embodiment, the methods use a local cleanup process to rewire the nodes between neighboring clock buffers to further reduce the amount of clock-gaters.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: February 26, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Zhuo Li, Charles Alpert, Brian Wilson
  • Patent number: 10210299
    Abstract: Disclosed are methods, systems, and articles of manufacture for dynamically abstracting virtual hierarchies for an electronic design. These techniques identify at least a portion of a layout of an electronic design and a virtual hierarchy in the layout portion according to a value for a display stop level. A plurality of figure groups at one or more virtual hierarchies in the layout portion may also be identified in the layout portion. These techniques select a plurality of layout circuit component designs according to the virtual hierarchy. The layout portion may then be abstracted into an abstracted layout portion at least by displaying the plurality of layout circuit component designs and suppressing one or more remaining layout circuit component designs.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 19, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Ginetti
  • Patent number: 10210301
    Abstract: A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Such pathways are routinely required for power and signal distribution purposes. Automated scripts perform a star routing methodology and validate the routing results. The methodology processes input width and layer constraints and from-to's denoting start and end points for each route by invoking a star_route command in a router that implements interconnections as specified. Routing results are validated by checking for routing violations, including shared segments and width violations. Violations are marked for correction.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 19, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ankur Chavhan, Devesh Jain, Behnam Farhat, Andrey Freidlin, Sundararajan Shanmugam, Susan Zueqing Zhang
  • Patent number: 10204180
    Abstract: Various embodiments implement an electronic design with automatically generated power intent. One or more inputs to a physical electronic design implementation module may be identified for power intent generation for an electronic design. The power intent for the electronic design may be generated by using at least one or more power related characteristics that are determined from at least the one or more inputs for the power intent generation. With the generated power intent, the electronic design may be implemented at least by guiding the implementation of the electronic design with at least the generated power intent while reducing usage of one or more computing resources.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kai-Ti Huang, Pinhong Chen, Richard M. Chou
  • Patent number: 10203875
    Abstract: A method to initiate Command Address (CA) training on High Memory Bandwidth is provided to optimize CA bus setup and hold times relative to the memory clock. HBM protocol does not define any way to support CA training, but defines a very high working frequency. The high frequency makes it very difficult to ensure the timing on CA Bus-Row/Column command bus and CKE. As such, executing CA training before any normal operation is necessary to ensure the best setup/hold timings. The CA training takes advantage of protocol based instructions to initialize and implement CA training.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Guangxi Ying, Zhehong Qian, Liang Huo, Yanjuan Zhan
  • Patent number: 10204187
    Abstract: An improved approach is provided to generate and display waveform data, where data reduction is intelligently applied to create filtered waveform data. By reducing the quantity of the waveform data in an intelligent manner, this permits the waveform display tool to process the waveforms quickly enough for interactive usage, while still retaining sufficient data fidelity for accurate data analysis and waveform visualization.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Iain Farquharson
  • Patent number: 10204201
    Abstract: Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Lawrence Loh, Artur Melo Mota Costa, Breno Rodrigues Guimaraes, Fabiano Peixoto, Andrea Iabrudi Tavares
  • Patent number: 10198539
    Abstract: Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tsair-Chin Lin, Jingbo Gao, Alon Kfir, Long Wang, Wei Zeng, Zhao Li
  • Patent number: 10198540
    Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation using a profiler. The method may include simulating, using a computing device, an electronic design associated with a programming language. The method may further include recording a first time corresponding to a first user-defined point in the simulation. The method may also include recording a second time corresponding to a second user-defined point in the simulation. The method may further include determining a difference in time between the first and second times and displaying a visualization including at least one of the first time, the second time, a value of a variable at the first time, a value of the variable at a second time, and the difference in time.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Daniel Asher Cohen
  • Patent number: 10198551
    Abstract: Systems, methods, media, and other such embodiments described herein relate to trimming cell lists prior to generation of a routing tree for a circuit design. One embodiment involves accessing a cell library including cell data and a cell list for a plurality of cells. Specialized delay cells are removed from the cell list, and remaining cells are analyzed to identify a set of cell characteristics. Cells are then trimmed from the cell list based on comparisons between the cell characteristics of the remaining cells. If certain cells are sufficiently similar, secondary characteristics can be used to further trim the cell list. The trimmed cell list can then be used to generate a routing tree for the circuit design according to associated design criteria.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amin Farshidi, Zhuo Li, Charles Jay Alpert, William Robert Reece