Abstract: An N-input (e.g., 4) multiplexor may receive N number of select signals. Select signal generating circuitry may receive N number of clock signals at a phase spacing that is substantially at 360 degrees divided by N (e.g., 90 degrees for N=4). The select signal generating circuitry may produce a coarse set of N number of select signals that may have unequal duty cycles and/or overlap. Duty cycle feedback control loops may be used to adjust respective duty cycles of the coarse select signals to produce select signals that have equal duty cycles and do not overlap.

Abstract: Multiple voltage amplitudes for an oscillator in a phase-locked loop may be selected to meet various design goals/criteria (e.g., frequency range of operation, jitter, power consumption, etc.). These multiple voltage amplitudes may be stored in a lookup table memory that relates frequency ranges to reference voltages. A reference voltage for a particular oscillator may then be selected and generated. A feedback loop may compare the amplitude output by the oscillator to the reference voltage and adjusts a bias current of the oscillator with the goal of substantially equalizing the oscillator output to the reference voltage.

Abstract: Various embodiments provide for verifying operation of a circuit design with respect to a data communication specification, such as a Peripheral Component Interconnect Express (PCIe) specification, using sequence numbers (e.g., fixed byte-size unit (FLIT) sequence numbers) of data packets (e.g., FLITs) to synchronize monitoring of data transactions over a data bus.

Abstract: Systems and methods for electronic design are provided. Embodiments may include causing a display of an electronic design at a graphical user interface and receiving via the graphical user interface, a user input connecting a first group including one or more scalar nets or buses with a symbolic representation of a second group including one or more scalar nets or buses. The first group and the second group may have an asymmetric structure. Embodiments may include performing an automatic connection assignment between the members of the first group and the second group.

Abstract: Embodiments included herein are directed towards a charge device model (“CDM”) protection circuit. The circuit may include a power supply, a power clamp operatively connected to the power supply, at least one diode connected with the power clamp, a field effect transistor (“FET”) operatively connected with the at least one diode and a trigger mechanism configured to activate the FET.

Abstract: The present disclosure relates to a dual mode, low dropout regulator circuit and method of using the same. The circuit may include a multiplexer configured to switch between a high-speed mode and a low-power mode and an error amplifier configured to generate an amplifier output. The circuit may include a class AB circuit configured to receive the amplifier output and generate a class AB output and a unity feedback circuit in electrical communication with the class AB circuit, wherein a single reference voltage is applied to perform a dual mode operation.

Abstract: Aspects of the present disclosure include system, methods, and software for buffer insertions. In one example, a method includes receiving a clock signal network layout, the clock signal network layout comprising a clock source electrically coupled to a plurality of clock sinks via a plurality of net segments, a first hierarchy that bounds a first region of the clock signal network layout, and a second hierarchy that bounds a second region of the clock signal network layout. The method additionally includes creating a graph representative of the clock signal network layout, the graph comprising a plurality of logical edges, and identifying a to-be-inserted buffer location comprising a location on a net segment of the plurality of net segments to insert a buffer. The method further includes selecting a selected logical edge to insert the buffer based on the to-be-inserted buffer location, the first hierarchy, the second hierarchy, or a combination thereof.

Abstract: Aspects of the present disclosure address systems and methods for zigzag detection and handling for integrated circuit designs. Data describing an integrated circuit is accessed. The integrated circuit design comprises a connection path between two or more pins of a net determined based on an initial routing of the net. A zigzag is detected in the connection path based on a local turn density constraint that specifies a ratio of a number of turns to a pathlength that corresponds to zigzagging in the net. In response to detecting the zigzag in the connection path, the zigzag is removed from the connection path by rerouting the net using a routing constraint that defines a maximum number of turns in the connection path.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design layout and performing parasitic extraction on the electronic design layout. Embodiments may further include extracting an electromagnetic model from the electronic design layout and reconnecting at least one coupling capacitor associated with a net of the electromagnetic model. Embodiments may include performing a simulation including the reconnected at least one coupling capacitor.

Abstract: Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described. The signaling compression associated with partially unrolled DFE results in multiplexers selecting a 1-bit output value from one of two 1-bit input values, which are decoding the actual multi-bit candidate levels and transforming the selected 1-bit output value to a multi-bit sliced value by adding to it a pointer value of a pulse-amplitude modulation (PAM) level. The signaling compression reduces the power and area of an N-tap DFE, where N is a positive integer.

Abstract: The present disclosure relates to a system and method for clock phase recovery. Embodiments may include sampling data using an in-phase clock and a quadrate phase clock. Embodiments may further include analyzing sampled data from the in-phase clock and the quadrate phase clock. Embodiments may also include determining a convergence point based upon, at least in part, the analyzed sampled data, wherein the convergence point corresponds to a point where a number of early sampled outcomes is approximately equal to a number of late sampled outcomes. Embodiments may also include dynamically updating an accumulator threshold based upon the convergence point.

Abstract: Embodiments include herein are directed towards various circuit topologies. A self-correcting latch circuit may include a plurality of memory loops, a plurality of clock inputs, a plurality of data inputs, and a plurality of outputs. Each of the plurality of memory loops may be configured to store data in parallel.

Abstract: An approach is disclosed herein a sequence generation ecosystem using machine learning. The approach disclosed herein is a new approach to sequence generation in the context of validation that relies on machine learning to explore and identify ways to achieve different states. In particular, the approach divides the valid operations into different respective actions and action sequences. These actions are selected by machine learning models as they are being trained using online inference reinforcement learning. This online inference also is likely to result in the discovery of new states. Each state that has been identified is then used as a target to train a respective machine learning model. As part of this process a representation of all the states and actions or sequences of actions executed to reach those states is created. This representation, the respective machine learning models, or a combination thereof can then be used to generate different test sequences.

Abstract: Systems and methods of collecting performance metrics of an emulated design are disclosed. A method includes receiving, by a processor in the emulation system from a host system, configuration data including one or more user defined parameters, connecting, by the processor, a performance monitor to a port between communicatively connected components in the emulation system, initiating, by the processor, an emulation of the DUT, receiving, by the processor, emulation data from the emulation system, calculating, by the processor, performance data based on the configuration data, filtering, by the processor, the emulation data based on the performance data, and outputting, by the processor, the filtered emulation data to the host system.

Abstract: The present disclosure relates to electronic circuit design, and more specifically, to training a neural network to serve as the reward function for optimization-based approaches to PCB design automation. Embodiments may include generating, using a processor, one or more placed designs using a genetic optimization methodology including a reward function and adjusting the one or more placed designs and the reward function during the generating. Embodiments may further include routing the one or more placed designs using an auto-router to assign a routability score label and training a neural network, using the one or more placed designs and the routability score label, to extract one or more intermediate features from the one or more placed designs. Embodiments may also include predicting a routability of the PCB design based upon, at least in part, the one or more intermediate features.

Abstract: Embodiments included herein are directed towards a method for visualizing an electronic circuit design. Embodiments may include causing a display of a portion of an electronic design at a graphical user interface and receiving, at the graphical user interface, a selection of an object to be moved, wherein the object is displayed in a first color. In response to a user input, embodiments may include moving the object at the graphical user interface nearer a target location, displaying at least one target type in a second color and snapping the object to the target location.

Abstract: A technical solution is directed to a clock recovery apparatus for multi-level signaling on a single-lane communication interface. The apparatus can use bin-map logic to successfully recover a common clock per symbol received on the multi-level signal interface. The multi-level signal can be PAM4 signaling where two bits are encoded to represent four levels. The clock recovery apparatus can detect signal level through individual edge detectors for each of the two bits and can handle jitter up to half-clock period.

Abstract: Aspects of the present disclosure address systems and methods for routing an integrated circuit design based on a maximum turn constraint. Data describing an integrated circuit is accessed. The integrated circuit design comprises a net specifying a connection between a first pin and a second pin. A maximum turn constraint is accessed. The maximum turn constraint specifies a maximum number of turns for connection paths generated in routing the integrated circuit design. The net is routed based on the maximum turn constraint. The routing of the net results in a routed net comprising a connection path between the first pin and the second pin that includes a number of turns that satisfy the maximum turn constraint. A layout instance for the integrated circuit design is generated based in part on the routed net.

Abstract: Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage domain and the first voltage domain. The methods and systems generate an output of the thin-oxide device interface using first and second thin-oxide devices, the output of the thin-oxide device interface having a range corresponding to the second voltage domain.

Abstract: Embodiments included herein are directed towards sampling circuits and methods of using the same. Embodiments may include a data sense amplifier circuit and a reference sense amplifier circuit directly connected with the data sense amplifier circuit. Embodiments may further include a latch circuit configured to receive a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit. The latch circuit may be further configured to generate a least significant bit output based upon, at least in part, the first input and the second input.