Patents Assigned to Cadence Design Systems, Inc.
  • Patent number: 10289775
    Abstract: Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may achieve this by identifying, after post-route-optimization, critical clock-tap-to-clock-device assignments based on timing analysis results (e.g., from AOCV/CPPR timing analysis) and feeding back those critical clock-tap-to-clock-device assignments to a process performing new clock tap assignments.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Brian Wilson, Charles Jay Alpert, Zhuo Li
  • Patent number: 10289793
    Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include receiving, using a processor, a parent fabric corresponding to a top layout fabric associated with an electronic design and receiving a child fabric corresponding to a child layout fabric associated with the electronic design. The method may further include receiving an electromagnetic (“EM”) model that represents one or more cross-fabric geometries associated with the electronic design and generating a hierarchical schematic representing each layout fabric, wherein the EM model is inserted into a parent schematic. The method may also include managing one or more interface connections between the hierarchical schematic.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taranjit Singh Kukal, Arnold Jean Marie Gustave Ginetti, Steven Roberts Durrill
  • Patent number: 10289774
    Abstract: Various embodiments describe performing static timing analysis (STA) on a circuit design such that delay timing calculation results generated by an STA on the circuit design can be reused by subsequent STAs on the circuit design in place of performing a set of delay timing calculations on the circuit design.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc
    Inventors: Pradeep Yadav, Ratnakar Goyal, Prashant Sethia, Manuj Verma
  • Patent number: 10289791
    Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include providing, using a processor, an electronic design having a plurality of shapes associated therewith and displaying, at a graphical user interface, a first shape of the plurality of shapes. Embodiments may further include receiving a selection of an anchor point within the first shape, wherein the anchor point defines a fixed area associated with the first shape. Embodiments may also include identifying a plurality of bend lines associated with the plurality of shapes and determining an ordering of bending of at least two of the plurality of shapes.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Reza Vossoughi
  • Patent number: 10289782
    Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include providing, using at least one processor, an electronic circuit design at a graphical user interface. Embodiments may further include associating one or more metrics with the electronic circuit design, wherein the one or more metrics include at least one of process metrics, design metrics, issues, library metrics, and custom metrics. Embodiments may further include allowing a user to specify one or more rules that define a key performance indicator for at least a portion of the electronic circuit design, wherein the key performance indicator is based upon, at least in part, the one or more metrics. After a design process associated with the electronic circuit design has been initiated, embodiments may include displaying the key performance indicator at the graphical user interface.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Rajesh Khanna, Matthew Timothy Bromley
  • Patent number: 10289795
    Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising a source, a plurality of sinks, and a skew threshold associated with the source and the plurality of sinks. An initial routing tree is generated between the source and the plurality of sinks, and then a first intermediate point is identified between the source and the plurality of sinks. The first intermediate point may be identified based on a median location of all sinks of the plurality of sinks, or other criteria. The first intermediate point is then used for an updated routing tree. In some embodiments, a process proceeds iteratively until the skew threshold is reached or a maximum wire length is exceeded.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jhih-Rong Gao, Thomas Andrew Newton, Derong Liu, Mehmet Can Yildiz, Charles Jay Alpert, Zhuo Li
  • Patent number: 10289780
    Abstract: Disclosed herein are systems and methods to perform electrical analysis of a circuit design to verify electrical behavior and performance of the circuit design in a two-step process. Initially, a simulator transient analysis is performed on circuit blocks of a circuit design to obtain a current through each device path in each circuit block, and using the current obtained the IR drop and EM problems are examined to get EM-IR drop analysis. Next, a simulator transient analysis is performed on a top level circuit of a circuit design and current values generated in a first step to obtain EM-IR drop analysis for a full circuit design such that a circuit designer may debug, analyze and visualize various IR and EM value plots for circuit blocks and top level circuit of the circuit design together or separately.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Babita C. Verma, Parveen Khurana, Sanjeev Azad, Xin Gu
  • Patent number: 10289798
    Abstract: The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ronalu Augusta Nunes Barcelos, Hudson Dyele Pinheiro de Oliveira, Mirlaine Aparecida Crepalde, Lucas Luz Reckziegel, Glauber Tadeu de Sousa Carmo, Augusto Amaral Mafra, Regina Mara Amaral Fonseca, Guilherme Henrique de Sousa Santos, Valdir Antoniazzi Júnior
  • Patent number: 10289764
    Abstract: Methods and systems are provided. In one aspect, a method for parallel extraction of worst case corners of a number of electronic design automation (EDA) simulations includes generating multiple initial EDA simulation results for a number of specifications of an integrated circuit based on a first algorithm. For each specification, a respective first set of input samples is generated based on a second algorithm using generated multiple initial simulation results. Using a third algorithm, two or more of the respective first set of input samples are merged based on a criterion to generate a respective second set of input samples. For each specification, a first set of simulation results is generated using the respective second set of input samples. The worst case corners for the specifications are determined by applying in parallel local optimization to the first set of simulation results.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hongzhou Liu, Wangyang Zhang
  • Patent number: 10289783
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include providing, using at least one processor, an electronic circuit design and generating a configuration associated with a portion of the electronic circuit design. Embodiments may further include associating a label with the configuration at a graphical user interface and applying the configuration to at least one of a design object, a sub-design, or the electronic circuit design. Embodiments may also include displaying the configuration and electronic design data associated with the configuration.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Rajesh Khanna, Matthew Timothy Bromley
  • Patent number: 10289788
    Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include storing one or more electronic circuit designs at an electronic circuit design database and receiving a user input associated with one of the electronic circuit designs. Embodiments may include scanning the one or more stored electronic circuit designs and generating a network including a relationship graph and a component map, based upon, at least in part, the scanning Embodiments may include generating at least one next neighbor component based upon, at least in part, the network and the received user input. Embodiments may include displaying one or more user-selectable options at a graphical user interface, wherein the user-selectable options include the at least one next neighbor component.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hitesh Mohan Kumar, Matthew Timothy Bromley, Vikas Kohli, Sagar Kumar
  • Patent number: 10289792
    Abstract: Various embodiments provide for clustering pins of a circuit design for connection to a power-ground network (PG) of the circuit design using a nearest neighbor graph. Pin clustering, according to some embodiments, can minimize wirelength, minimize a number of vias, satisfy constraints relating to a pin count (e.g., maximum number of pins per power-ground access point), and satisfy constraints relating to a bounding box size.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wing-Kai Chow, Wen-Hao Liu, Gracieli Posser, Mehmet Can Yildiz
  • Patent number: 10289797
    Abstract: Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of neighboring clusters that fail or nearly fail to satisfy design rule constraints are dissolved and corresponding pins are regrouped to form new clusters that satisfy design rule constraints.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Natarajan Viswanathan, Charles Jay Alpert, Wen-Hao Liu, Thomas Andrew Newton
  • Patent number: 10290107
    Abstract: Aspects of the present disclosure involve a transform domain regression convolutional neural network for image segmentation. Example embodiments include a system comprising a machine-readable storage medium storing instructions and computer-implemented methods for classifying one or more pixels in an image. The method may include analyzing the image to estimate one or more transform domain coefficients using a multi-layered function such as a convolutional neural network. The method may further include generating a segmented image by applying a change of basis transformation to the estimated one or more transform domain coefficients.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Raúl Alejandro Casas, Samer Lutfi Hijazi, Rishi Kumar, Piyush Kaul, Xuehong Mao, Christopher Rowen, Himanshu Charaya
  • Patent number: 10282250
    Abstract: Embodiments of the invention provide an apparatus and method for a coherent, efficient, and configurable cyclic check redundancy retry implementation for synchronous dynamic random access memory. The process includes storing write commands as groups of bursts in a storage location where those commands are stored at least until a time frame has passed for receiving a corresponding cyclic redundancy check failure message. In some embodiments, the process includes retrying corresponding groups of bursts after receiving a failure message where retried groups of bursts are given priority over other memory access commands. In some embodiments, when a read command is received corresponding to a write command that is not beyond the relevant time frame the read command will also be held back from execution until the corresponding time frame has passed without notification of cyclic redundancy check value failure.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 7, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bikram Banerjee, Anne Rodgers Hughes, John Michael MacLaren
  • Patent number: 10282501
    Abstract: A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a prototyping platform to stop when the assertion control signal is enabled in the assertion checker and a logic condition for the assertion control signal is satisfied in the prototyping platform. A system and a computer readable medium including instructions to perform the above method are also provided.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 7, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Vasant Ramabadran
  • Patent number: 10285276
    Abstract: A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 7, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Taranjit Kukal, Arnold Ginetti, Steven R. Durrill, Abhay Agarwal, Vikas Kohli, Tyler Lockman
  • Patent number: 10282505
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing legal routing tracks across virtual hierarchies and legal placement patterns. These techniques identify at least a layout or a portion thereof and determine one or more legal sets of routing tracks for the layout or the portion. One or more figure groups are identified or generated at a first virtual hierarchy, and the one or more first figure groups inherit respective portions of the one or more legal sets of routing tracks. A plurality of legal devices are identified in a layout or a portion thereof, and a figure group is generated at least by determining a boundary for the figure group and enclosing the plurality of layout devices within the boundary. These techniques may modify a placement row without disturbing compliance of one or more design rules with which the legal device pattern complies when generated.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 7, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Ginetti
  • Patent number: 10282206
    Abstract: According to certain general aspects, the present embodiments allow register files and states with different data types to share logic area while minimizing unnecessary use of power in a configurable processor. Embodiments include allowing configurable processor designers to describe alias register files and states. Using alias register files and states, designers can implement vector and scalar operations on different register files, but the scalar register file can be implemented on the vector register file. In addition, the upper lanes of the vector register file can be clock gated when the scalar operation performs computations. With this gating, the clocks for the entire upper lanes (including the register file, state, semantic, mux, decoder) can be disabled, which provides power savings.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: May 7, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Fei Sun, Tiansi Hu
  • Patent number: 10282506
    Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of clock routing trees. One embodiment involves accessing a circuit design and a clock tree hierarchy input indicating a nested list of partition or sink groups, each group of the nested list of groups comprising one or more clock tree elements of a plurality of clock tree elements from the circuit design. A routing topology associated with a source and a plurality of sinks are determined based on an ordering within the nested list of partition groups. These routing directions are used in synthesizing a clock tree for the circuit design. In additional embodiments, the clock tree hierarchy input provides clustering information, port placement for connections between partition groups of the clock tree, and parameters describing limitations or criteria for individual partition groups.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 7, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dirk Meyer, Zhuo Li, Charles Jay Alpert