Patents Assigned to Cadence Design Systems, Inc.
  • Patent number: 11983538
    Abstract: Techniques are disclosed relating to a processor load-store unit. In some embodiments, the load-store unit is configured to execute load/store instructions in parallel using first and second pipelines and first and second tag memory arrays. In tag write conflict situations, the load-store unit may arbitrate between the first and second pipelines to ensure the first and second tag memory array contents remain identical. In some embodiments, a data cache tag replay scheme is utilized. In some embodiments, executing load/store instructions in parallel with fills, probes, and store-updates, using separate but identical tag memory arrays, may advantageously improve performance.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: May 14, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert T. Golla, Ajay A. Ingle
  • Patent number: 11979264
    Abstract: Methods and systems are provided for processing a signal over a serial link. The methods and systems receive, by an adjustable filter, a serial input signal, the adjustable filter configured to set a corner frequency of a channel response and a gain of the channel response, the adjustable filter adding a zero to the channel response before to a pole of the serial input signal. The methods and systems selectively apply, by a bandwidth booster component, compensation to signal attenuation of the serial input signal in a first mode of operation and of one or more test signals in a second mode of operation of a serial link receiver. The methods and systems generate, by one or more continuous time linear equalizers configured to receive on an output of the bandwidth booster, one or more output signals of the receiver based on an output signal from the bandwidth booster component.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: May 7, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Riju Biswas, Abhishek Shrivastava
  • Patent number: 11979262
    Abstract: Various embodiments provide for identifying and training a floating tap for decision feedback equalization. For some embodiments, the identification and training of the floating tap described herein can be part of a circuit for receiver block of a system, such as a memory system.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: May 7, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hari Anand Ravi, Sachin Ramesh Gugwad
  • Publication number: 20240143877
    Abstract: Disclosed is an improved approach to implement sharing of delay calculations for replicated portions of a design, where input slews may be different between those replicated design portions. This allows the system to experience runtime improvements for timing analysis of electronic designs.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Applicant: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Nikita Sergeev, Pradeep Yadav, Maksim Baranov
  • Patent number: 11971818
    Abstract: A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic value. The memory view file has an address limit characterizing a number of words in the NVM module and an address partition characterizing address bits and data bits. The memory view file includes a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 30, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven L. Gregor, Puneet Arora
  • Patent number: 11966633
    Abstract: An NVM algorithm generator that evaluates a Liberty file characterizing an NVM module and a memory view of the NVM module that identifies ports and associated operations of the NVM module to generate a control algorithm. The control algorithm includes a read algorithm that includes an order of operations for assigning values to ports of the NVM module to assert a read condition of a strobe port, executing a memory read on the NVM module and setting values to the ports on the NVM module to assert a complement of a program condition. The control algorithm also includes a program algorithm that includes an order of operations for assigning values to ports of the NVM module to assert the program condition of the strobe port, executing a memory write and setting values to the ports on the NVM module to assert the complement of the program condition.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 23, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven L. Gregor, Puneet Arora
  • Patent number: 11960351
    Abstract: Systems and methods for propagating poison information are provided. Embodiments include receiving write data having a poison flag asserted indicating the data to be written to a memory device is erroneous. Embodiments further include converting the write data to a pre-fixed data pattern and generating a parity code, based upon, at least in part, the pre-fixed data pattern. Embodiments may also include injecting a correctable error into the write-data or parity code and writing the write data and parity code into the memory device. The correctable error injection may occur in the data or in the parity code and during the read the comparison may occur accordingly.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: April 16, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dipakkumar Trikamlal Modi, Bikram Banerjee, Maddula Balakrishna Chaitanya
  • Patent number: 11960400
    Abstract: A cache memory circuit capable of dealing with multiple conflicting requests to a given cache line is disclosed. In response to receiving an acquire request for the given cache line from a particular lower-level cache memory circuit, the cache memory circuit sends probe requests regarding the given cache line to other lower-level cache memory circuits. In situations where a different lower-level cache memory circuit is simultaneously trying to evict the given cache line at the particular lower-level cache memory circuit is trying to obtain a copy of the cache line, the cache memory circuit performs a series of operations to service both requests and ensure that the particular lower-level cache memory circuit receives a copy of the given cache line that includes any changes in the evicted copy of the given cache line.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: April 16, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert T. Golla, Matthew B. Smittle
  • Patent number: 11947887
    Abstract: A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: April 2, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Krishna Chakravadhanula, Brian Foutz, Prateek Kumar Rai, Sarthak Singhal, Christos Papameletis, Vivek Chickermane
  • Patent number: 11941334
    Abstract: Embodiments include herein are directed towards a system and method for intelligent intent recognition based electronic design. Embodiments may include receiving, using a processor, a natural language input from a user at an intent recognition model. Embodiments may also include performing intent recognition on the natural language input at the intent recognition model and providing an output from the intent recognition model to a command generator. Embodiments may further include generating a command based upon, at least in part, the output and executing the command at a target tool environment.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Deepak Gupta, Hitesh Mohan Kumar, Yatinder Singh
  • Patent number: 11941335
    Abstract: Methods and systems for providing concise data for analyzing checker completeness, in the context of formal verification analysis of circuit designs. The methods and systems concisely report information useful to a human user (e.g., circuit designer or verification engineer) for efficiently determining what manual action should be taken next to resolve holes in verification coverage. The reported information can include lists of signals on which checkers can be written, which lists can be ranked, can be limited to a subset of interest signals, and can include corresponding cover items for each reported interest signal. The present systems and methods thereby improve on reporting provided to the user, permitting the user to more quickly advance a formal verification process toward full coverage of the relevant portions of a circuit design.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: March 26, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Verma, Yumi Monma, David Spatafore, Suyash Kumar, Devank Jain
  • Patent number: 11936353
    Abstract: A current-mode transmitter amplifies a differential input signal to a differential, current-mode output signal. A split-input, current-mode-logic stage produces small, analog signals to limit switching currents and thus power consumption and power-supply noise. These small, analog signals are driven through a source-follower stage to reduce loading and shift the common-mode voltage to a desired level. A switched-current-source H-bridge driver combines differential outputs from the source-follower stage to provide an amplified differential output current. The output swing from the H-bridge driver is controlled by the voltage level from the source follower and derived from a replica-bias structure.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: March 19, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Eric Douglas Groen, Charles Walter Boecker
  • Patent number: 11934269
    Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: March 19, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Kedia, Kartik Dayalal Kariya, Sreeja Menon, Steven C. Woo
  • Patent number: 11928027
    Abstract: Embodiments include receiving fixed size error checking and correction data blocks and metadata at a memory controller. Embodiments may include performing data to symbol mapping based upon the fixed size data blocks and providing an output of the data to symbol mapping to a first encoder without metadata configured for full detection correction of single device error and to a second encoder with metadata configured for partial detection correction of single device error. Embodiments may include receiving data at a memory based upon an output from the first encoder and the second encoder and receiving data from the memory at a first decoder without metadata configured for full detection correction of single device error and at a second decoder with metadata configured for partial detection correction. Embodiments may include re-mapping symbol data from the first decoder and the second decoder to actual data and generating output data blocks and metadata.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 12, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Modi Dipakkumar Trikamlal, Maddula Balakrishna Chaitanya
  • Patent number: 11928582
    Abstract: Embodiments of the invention provide a system, media, and method for deep learning applications in physical design verification. Generally, the approach includes maintaining a pattern library for use in training machine learning model(s). The pattern library being generated adaptively and supplemented with new patterns after review of new patterns. In some embodiments, multiple types of information may be included in the pattern library, including validation data, and parameter and anchoring data used to generate the patterns. In some embodiments, the machine learning processes are combined with traditional design rule analysis. The patterns being generated and adapted using a lossless process that encodes the information of a corresponding area of a circuit layout.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 12, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Piyush Pathak, Haoyu Yang, Frank E. Gennari, Ya-Chieh Lai
  • Patent number: 11928410
    Abstract: Methods and systems are disclosed for optimizing compilation efforts for design debug based on formal analyses. The method includes accessing a circuit design, automatically determining a segment as being a design region of interest, identifying a behavior within the segment for performing at least one verification test, compiling the segment without compiling a remainder of the circuit design, and providing performance indicators corresponding to the behavior within the segment based on the segment as compiled.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Stefano Mano, Yumi Monma
  • Patent number: 11928045
    Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include simulating a processor model and a hardware model, each executed with a corresponding simulator thread on a simulation platform. Embodiments may also include simulating embedded software using the processor model. The simulating may include updating a given register of the processor model that stores a value that changes in response to switching between processes within the embedded software. Embodiments may further include setting a simulator breakpoint and a software breakpoint and enabling debugging of both non-virtual and virtual addresses at the software breakpoint without leaving the software breakpoint.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: March 12, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bishnupriya Bhattacharya, Andrew Robert Wilmot, Zhiting Duan, Neeti Khullar Bhatnagar
  • Patent number: 11928500
    Abstract: Various embodiments provide for multi-threaded network routing of a circuit design based on partitioning networks of the circuit design, which can enable partitioning routing tasks for the circuit design. More particularly, some embodiments iteratively partition networks of a circuit design into groups of networks, which enable various embodiments to schedule routing tasks for those groups of networks to available threads such that no two networks of the circuit design with overlapping routing regions are routed at the same time, and such that idle time of each thread (e.g., time where thread has no work or is waiting for another thread to finish) can be minimized.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: March 12, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wing-Kai Chow, Mehmet Can Yildiz
  • Patent number: 11909565
    Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. In embodiment, a single-ended receiver trains DFE coefficients and the slicer reference voltage to improve the received eye height. The process for training avoids many whole range sweeps thereby shortening training time. A custom data pattern that includes low-frequency (DC with respect to DFE) and high-frequency (AC with respect to DFE) worst cases is used for training in a closed loop manner. Negative DFE is used to measure the AC height of the data. Positive DFE is used to find the DC height of the data pattern.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: February 20, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Anirudha Shelke, Ashwin S. Madhavakaimal, Kiran Baby
  • Patent number: 11900135
    Abstract: An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: February 13, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G Poplack, Yuhei Hayashi