Patents Assigned to Cadence Design Systems, Inc.
  • Patent number: 11620548
    Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having an original schematic associated therewith and extracting one or more features for each net from the schematic. Embodiments may include storing one or more resistance or capacitance values for each net and applying the one or more resistance or capacitance values as labels for a machine learning model. Embodiments may also include training the machine learning model using one or more actual values to generate a trained model. Embodiments may further include receiving the trained model to predict parasitics for a stitching engine and generating a stitched schematic.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: April 4, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sai Bhushan, Elias Lee Fallon, Chirag Ahuja
  • Patent number: 11620428
    Abstract: Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to update the clock tree. An indication is provided that the updated clock tree has been modified and complies with the target timing offset.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: April 4, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andrew Mark Chapman, Zhuo Li
  • Patent number: 11620417
    Abstract: Aspects of the present disclosure address systems, methods, and a user interface for providing interactive skew group visualizations for integrated circuit (IC) design. The method includes causing display of a user interface that includes a display of a grouped view of a clock-tree including a plurality of skew group indicators. The method further includes receiving a user selection of a skew group indicator and updating the user interface to display a detailed view of the skew group including a graphical representation of each clock sink in the skew group and corresponding timing information. The method further includes receiving a second user selection of a first clock sink and in response, the display is updated to display an indicator of a physical location of the first clock sink within the clock tree.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 4, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ainsley Malcolm Pereira, Thomas Andrew Newton
  • Patent number: 11615320
    Abstract: An approach includes identification of a machine learning model for processing and generating an ordered set of weights with varying precisions and metadata that specifies where those values can be found in order to allow the identification of weights needed during processing. In a first embodiment, the variable precision weights are separated into different memory segments where each segment has weights of only a single precision. In a second embodiment, the variable precision weights are provided in a memory where weights of different precisions are intermingled, and those weights are identified using a sequence of pairs of data representing a number of weights with the same precision and the precision of those weights. In some embodiments, both the first and second embodiments are combined, where some segments contain weights with only a single precision and at least one segment stores weights with different precisions within a respective segment.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 28, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ngai Ngai William Hung, Dhiraj Goswami, Michael Patrick Zimmer, Yong Liu
  • Patent number: 11615229
    Abstract: An approach includes a new power and ground structure description language (PSDL) will allow the user to describe the desired routing pattern for each layer and on a user defined region by region basis, including how the pattern will be laid out in the design with respect to other patterns from a different layer. The new PSDL also gives the complete picture of the entire power and ground structure, instead of just a layer-by-layer view from a single command. It also allowed flexibility in alignment especially when dealing with track misalignments, thus avoiding the extensive trial-and-error steps needed to calculate offsets and distances to maintain pattern alignment using previous approaches. Additionally, because PSDL is not tightly dependent on the design size and/or floorplan, transferring the desired power and ground structure from one design to another will be very easy with only few adjustments.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 28, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Stefanus Mantik, Jianmin Li, Dennis Jenhsin Huang, Dewi Farrah Santoso, Ting Li, Ming Zhang
  • Patent number: 11610040
    Abstract: Embodiments disclosed herein describe switching logic in board-level interconnects and in the system-level interconnects that may provide bitwise dynamic routing and switching between corresponding board-level and system-level components. At board-level, a switching ASIC may receive input data through a backplane from an emulation ASIC in a first logic board and route any bit of the input data to any of the emulation ASIC in a second logic board. At system-level, a switching logic board containing a set of switching ASICs may be associated with a logic cluster and may dynamically route data bits from the emulation ASICs in the logic cluster to emulation ASICs to other logic clusters of the emulation system and/or target systems. Additionally, the switching logic board may dynamically route bits from the other logic clusters to the associated logic cluster.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: March 21, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Barton Quayle, Mitchell G. Poplack
  • Patent number: 11599699
    Abstract: The present disclosure relates to systems and methods for floorplanning using machine learning techniques. Embodiments may include receiving an electronic design and analyzing the electronic design using a reinforcement learning agent. Embodiments may further include recommending a first action wherein the first action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the electronic design based upon, at least in part, the first action to generate an updated electronic design. Embodiments may further include analyzing the updated electronic design using the reinforcement learning agent and recommending a second action wherein the second action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the updated electronic design based upon the second action to generate a second updated electronic design.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 7, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Luke Roberto, Joydeep Mitra, Taylor Elsom Hogan, Shang Li, Zachary Joseph Zumbo, John Robert Murphy
  • Patent number: 11593437
    Abstract: The present disclosure relates to a system and method for electronic design. Embodiments may include receiving, using at least one processor, a plurality of distinct electronic designs at an electronic design database and storing the plurality of distinct electronic designs at the electronic design database. Embodiments may further include receiving a request to reuse one of the plurality of distinct electronic designs from a client electronic device associated with a user, wherein the request includes design connectivity information, block connectivity information, and page connectivity information. Embodiments may also include analyzing the design connectivity information, block connectivity information, and page connectivity information to identify one or more closest matches with the plurality of distinct electronic designs and providing the one or more closest matches to the client electronic device to allow for subsequent displaying at a graphical user interface.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 28, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Daniel Konrad Fernsebner, Vikas Kakkar, Vikas Kohli, Mark Joseph Hepburn
  • Patent number: 11592482
    Abstract: Scan channel slicing methods and systems for testing of scan chains in an integrated circuit (IC) reduce the number of test cycles needed to effectively test all the scan chains in the IC, reducing the time and cost of testing. In scan channel slicing, rather than loading and unloading into scan chains high-power patterns having numerous switching transitions over the length of each scan chain, loading and unloading the entirety of the scan chain scan while observing it, chain load data is sliced, apportioning between the different scan chains independently observable sections (slices) of transition data in which all four bit-to-bit transitions (“0” to “0”, “0” to “1”, “1” to 0”, “1” to “1”) are ensured to exist. The remainder of the scan chain load data, which is not observed in the test procedure, can be low-transition data that consumes low dynamic power, such as mostly zeroes or mostly ones.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: February 28, 2023
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sameer Chakravarthy Chillarige, Anil Malik, Bharath Nandakumar
  • Patent number: 11579194
    Abstract: An integrated circuit (IC) test engine can generate a plurality of single cycle test patterns that target a plurality of static single cycle defects of a fabricated IC chip based on an IC design. The IC test engine can also fault simulate the plurality of single cycle test patterns against a plurality of multicycle defects in the IC design, wherein a given single cycle test pattern of the plurality of single cycle test patterns is sim-shifted to enable detection of a given multicycle fault and/or defect of the plurality of multicycle faults and/or defects.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: February 14, 2023
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Arvind Chokhani, Joseph Michael Swenton, Martin Thomas Amodeo
  • Patent number: 11580284
    Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and performing a deadlock check on the electronic circuit design using a using a linear temporal logic property and a proof engine. Embodiments may further include analyzing a counterexample associated with the electronic circuit design for a loop escape condition, wherein analyzing includes proving a cover trace of a liveness obligation. If the loop escape condition is reachable from the counterexample, embodiments may include extracting one or more events associated with the loop escape condition and adding a waiver constraint to the deadlock check to force a no deadlock outcome.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: February 14, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Craig Franklin Deaton, Christopher William Komar, Lars Lundgren
  • Patent number: 11573883
    Abstract: A trace subsystem of an emulation system may generate differential frame data based upon successive frames. If one compression mode, the trace subsystem may set a flag bit and store differential frame data if there is at least one non-zero bit in the differential frame data. If the differential frame data includes only zero bits, the trace subsystem may set the flag bit without storing the frame data. In another compression mode, the computer may further compress the differential data if the frame data includes one (one-hot) or two (two-hot) non-zero bits. The controller may set flag bits to indicate one of all-zeroes, one-hot, two-hot, and random data conditions (more than two non-zero bits). For one-hot or two-hot conditions, the controller may store bits indicating the positions of the non-zero bits. For random data conditions, the controller may store the entire differential frame.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 7, 2023
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Mitchell G. Poplack, Aruna Aluri, Linwei Ding
  • Patent number: 11568923
    Abstract: A device, a memory interface device, and a method of implementing an active inductor circuit are disclosed. In one aspect, the device includes one or more active inductor circuits, each including a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first MOS transistor has a first terminal connected to a first voltage level, a second terminal connected to a resistor, and a gate terminal. The second MOS transistor has a first terminal connected to the first voltage level, a second terminal connected to a first current source and the gate terminal of the first MOS transistor, and a gate terminal connected to the resistor and to a capacitor connected to a second voltage level. One of the first MOS transistor and the second MOS transistor is a p-channel MOS (PMOS) transistor, and another of the first MOS transistor and the second MOS transistor is an n-channel MOS (NMOS) transistor.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: January 31, 2023
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Hajee Mohammed Shuaeb Fazeel, Vinod Kumar
  • Patent number: 11562110
    Abstract: A system, method, and computer program product for predicting mismatch contribution in an electronic environment. Embodiments may include modeling, using a processor, a discrete output mismatch contribution problem using sparse logistic regression to generate a mismatch contribution model and applying a cross-validation approach to increase a complexity of the mismatch contribution model. Embodiments may further include computing one or more mismatch contribution values from the mismatch contribution model and defining at least one sizing constraint or determining a worst case result associated with a sampling process based upon, at least in part, the one or more mismatch contribution values.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: January 24, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Hongzhou Liu, Hua Luo, Elias Lee Fallon
  • Patent number: 11550980
    Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving one or more user defined processor configurations at a processor generator. Embodiments may also include generating a customized testbench based upon, at least in part, the user defined processor configurations and generating an RTL model while the customized testbench is generating.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: January 10, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tahrina Hossain Ahmed, Mohammad Rashedul Islam, Lishen Yin, Xin Fang, Khondakar Ahmed Mujtaba
  • Patent number: 11545968
    Abstract: Various embodiments provide for active suppression circuitry. The active suppression circuitry can be used with a circuit for a memory system, such as a dual data rate (DDR) memory system. For example, some embodiments provide an active suppression integrated circuit. The active suppression integrated circuit can be used by a memory system to efficiently suppress power supply noise caused by resonance of a power delivery network (PDN) of the memory system, thereby improving power integrity of the memory system input/output.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: January 3, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Moo Sung Chae, Thomas Evan Wilson
  • Patent number: 11544574
    Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and optionally an electronic design layout. Embodiments may further include analyzing the electronic design schematic to determine if one or more required features of a particular circuit structure are present. If the one or more required features are present, embodiments may include analyzing, using a machine learning model, the electronic design schematic to determine if one or more optional features of the particular circuit structure are present.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 3, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Elias Lee Fallon
  • Patent number: 11537505
    Abstract: The present disclosure is directed to a mechanism for forcing a processor to enter a debug mode. In one embodiment, a processor includes a logic circuit configured to receive a halt request. In response to receiving the halt request while the processor is not in a quiescent state, the logic circuit forces the processor into the quiescent state after a threshold amount of time has elapsed. Processor operation is then halted, and the processor thus becomes accessible for a debugger to perform debug operations.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: December 27, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert T. Golla, Matthew B. Smittle
  • Patent number: 11531550
    Abstract: Techniques are disclosed relating to an apparatus that includes a plurality of execution pipelines including first and second execution pipelines, a shared circuit that is shared by the first and second execution pipelines, and a decode circuit. The first and second execution pipelines are configured to concurrently perform operations for respective instructions. The decode circuit is configured to assign a first program thread to the first execution pipeline and a second program thread to the second execution pipeline. In response to determining that respective instructions from the first and second program threads that utilize the shared circuit are concurrently available for dispatch, the decode circuit is further configured to select between the first program thread and the second program thread.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: December 20, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert T. Golla, Christopher Olson
  • Patent number: 11531803
    Abstract: A static timing analysis system for finding and reporting timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use exhaustive path-based analysis (EPBA) that is informed by infinite-depth path-based analysis (IPBA) to provide analysis results that are driven full-depth, in contrast to conventional EPBA systems and methods, which can terminate after reaching a maximum depth of analysis as a way of avoiding prolonged or infinite runtimes. The IPBA-driven full-depth EPBA functions for hold-mode as well as setup-mode analysis and achieves reduced pessimism as compared to systems or methods employing IPBA alone, and more complete analysis of designs as compared to systems or methods employing EPBA alone. Improved IPBA signal merging using multidimensional zones for thresholding of signal clustering mitigates the occasional optimism of IPBA.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 20, 2022
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Umesh Gupta, Naresh Kumar, Marut Agarwal, Rakesh Agarwal