Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving a selection of an instance associated with an electronic design at an electronic design schematic displayed on a graphical user interface. Embodiments may also include selecting a corresponding instance within an electronic design layout displayed on a graphical user interface. Embodiments may further include receiving a selection of a source topology and routing at the electronic design layout displayed on the graphical user interface, based upon at least in part, the source topology.

Abstract: The present disclosure relates to packing transaction layer (TL) packets at a link layer of a protocol stack. In some examples, channel type data identify a type of message channel for a first TL packet can be generated. A set of slot formats for a slot for packing the first TL packet can be identified based on the channel type data and a slot format database. A respective slot format of the set of slot formats can be selected for the slot based on a message type of the first TL packet, and a message type of a second TL packet. The first TL packet and the second TL packet can be packed into the slot having the selected respective slot format during generation of a link layer packet.

Abstract: An integrated circuit that includes a feedback loop to adapt receiver parameters. The feedback loop includes a receiver to sample a signal and produce a sampled signal sequence. The feedback loop also includes a first pattern counter to detect and count occurrences of a first pattern in the sampled signal sequence, and a second pattern counter to detect and count occurrences of a second pattern in the sampled signal sequence. Control circuitry coupled to the receiver adapts a parameter value of the receiver to minimize a difference between a first ratio and a second ratio. The first ratio is a target ratio. The second ratio is between a first counted number of occurrences of the first pattern in the sampled signal sequence and a second counted number of occurrences of the second pattern in the sample signal sequence.

Abstract: The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.

Abstract: An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate. The ISI estimate from each stage is further equalized by application of the measures of low-frequency ISI from the first feed-forward stage and fed to the next in the cascade of stages. The ISI estimates from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.

Abstract: Embodiments included herein are directed towards a transmitter circuit. The circuit may include a most significant bit (“MSB”) main driver and a most significant bit boost driver operatively connected to the MSB main driver. The circuit may also include a least significant bit (“LSB”) main driver and a least significant bit boost driver operatively connected to the LSB main driver, wherein the MSB main driver and the LSB main driver are configured to receive two parallel non-return-to-zero (“NRZ”) data inputs.

Abstract: Implementations may include a method of accelerated modification of an emulation processor system, by loading, by a first emulation processor, a first portion of processor instructions into one or more registers of the first emulation processor, in response to a selection of a first programming mode associated with the first emulation processor, and loading, by a second emulation processor operatively coupled with the first emulation processor, a second portion of the processor instructions into one or more registers of the second emulation processor, in response to a selection of a first programming mode associated with the second emulation processor.

Abstract: Various embodiments provide for context-aware circuit design layout construct, which may be part of electronic design automation (EDA). In particular, some embodiments enable use of a circuit design layout construct with a layout of a circuit design (hereafter, a circuit design layout), where a programmable pattern of layout shapes of the circuit design layout construct can be inserted into a circuit design layout and can be adapted based on context information associated with the location of its placement within the circuit design layout.

Abstract: Aspects of the present disclosure address systems and methods for driver resizing using a transition-based capacitance increase margin. An integrated circuit (IC) design stored in a database in memory is accessed. The IC design comprises a net comprising a set of driver cells. A capacitance increase margin for resizing an initial driver cell is determined based on a total capacitance of the net and transition time target associated with the initial driver cell. An alternative driver cell is selected from a library to resize the initial driver cell and is used to replace the initial driver cell in the net. The alternative driver is selected such that a pin capacitance of the alternative driver cell exceeds an initial pin capacitance corresponding to the initial driver cell by no more than the capacitance increase margin.

Abstract: A method for optimizing a verification regression includes obtaining data, by a processor, of previously executed runs of at least one verification regression session; extracting from the data, by the processor, values of one or a plurality of control knobs and values of one or a plurality verification metrics that were recorded during the execution for each of the previously executed runs of said at least one verification regression; finding, by the processor, correlation between said one or a plurality of the control knobs and each said one or a plurality of verification metrics, and generating a set of one or a plurality of control conditions based on the found correlation; and applying, by the processor, the generated set of one or a plurality of control conditions on the verification environment or on the DUT, or on both, to obtain a new verification regression session.

Abstract: Disclosed is a method and system for visualizing schematic changes for an electronic design, where multiple schematic view interfaces are provided such that a first schematic interface displays an older schematic version and a second schematic interface displays a newer schematic version. Coordination is performed between the multiple schematic views such that an element within any of the first or second schematic views is appropriately highlighted based upon a user input.

Abstract: Quantized softmax layers in neural networks are described. Some embodiments involve receiving, at an input to a softmax layer of a neural network from an intermediate layer of the neural network, a non-normalized output comprising a plurality of intermediate network decision values. Then for each intermediate network decision value of the plurality of intermediate network decision values, the embodiment involves: calculating a difference between the intermediate network decision value and a maximum network decision value; requesting, from a lookup table, a corresponding lookup table value using the difference between the intermediate network decision value and the maximum network decision value; and selecting the corresponding lookup table value as a corresponding decision value. A normalized output is then generated comprising the corresponding lookup table value for said each intermediate network decision value of the plurality of intermediate network decision values.

Abstract: Various embodiments provide for quantizing a trained neural network with removal of normalization with respect to at least one layer of the quantized neural network, such as a quantized multiple fan-in layer (e.g., element-wise add or sum layer).

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include enabling data transmission between plurality of protocol adapters, each of the protocol adapters including one ingress port and one egress port, wherein the ingress port of each of the plurality of protocol adapters maintains an active connection with a single egress port at one time. Embodiments may further include transmitting data between the plurality of protocol adapters using a distributed routing matrix that provides an interface between the plurality of protocol adapters.

Abstract: An approach is disclosed herein for dynamic design switching for high performance mixed signal simulation. Disclosed herein is a new approach to simulation processes that allows for different segments of a design to be swapped out without requiring re-elaboration. This is an improvement over current techniques and decreases the amount of time need to simulate a design. In some embodiments, the technique illustrated herein is combined with an automated triggering mechanism that controls the selection of alternate representations for the same element base on those triggers. In some embodiments a new multiplexor structure is provided that is specifically tailored to solving the present issue.

Abstract: Various embodiments provide for predicting a simulation result for a circuit design using a machine learning model, which can be used as part of a process of an electronic design automation (EDA) system that measures a circuit design (e.g., timing, power, voltage, current, etc.). In particular, various embodiments described herein can enable modeling simulated time measurements of a circuit design, and can enable such modeling with minimal usage of simulation result data.

Abstract: A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.

Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.

Abstract: A tuned single-coil inductor is implemented between a signal driver output and external contact of an ESD-protected integrated circuit (IC) die and more specifically between the parasitic capacitances of the signal driver and the contact-coupled ESD (electrostatic discharge) element to form a Pi (?) filter that enhances signaling bandwidth at the target signaling rate of the IC die. The signal driver may be implemented with output-stage data serialization circuitry disposed in series between source terminals of a thick-oxide drive transistor and a power rail to avoid explicit level-shifting circuitry between the relatively low core voltage domain and relatively high I/O voltage domain.

Abstract: A decision-feedback equalizer (DFE) samples an input signal with respect to a gamut of p reference-voltage levels to place the symbol represented by the input signal within a voltage region. The DFE derives a set of tentative decisions for the voltage region, the set excluding at least one of the possible values for the symbol under consideration. A feedback stage then selects a final decision from among the tentative decisions.