Abstract: Periodic signal timing calibration is implemented in time-distributed fragments executed concurrently with occasional system-idling maintenance operations to maintain reliable synchronous communication between interconnected system components without impacting system availability.

Abstract: A queue circuit that manages access to a memory circuit in a computer system includes multiple sets of entries for storing access requests. The entries in one set of entries are assigned to corresponding sources that generate access requests to the memory circuit. The entries in the other set of entries are floating entries that can be used to store requests from any of the sources. Upon receiving a request from a particular source, the queue circuit checks the entry assigned to the particular source and, if the entry is unoccupied, the queue circuit stores the request in the entry. If, however, the entry assigned to the particular source is occupied, the queue circuit stores the request in one of the floating entries.

Abstract: An approach is disclosed herein to sequence selection in a UVM environment. Generally, this approach includes a training phase for each machine learning model of a plurality of machine learning models. Each model is trained to achieve a particular target state and is rewarded when a selected action or sequence of actions causes movement that might be beneficial to achieving that target state. Once a respective model is trained, the trained model can then be used to determine which one action or sequence of actions (or ordered multiple thereof) to take to achieve the corresponding target state. Thus, by training and using a plurality of machine learning models to achieve a plurality of target states, and stimulating those machine learning models once trained, one or more actions and/or sequences of actions are generated as the selected sequences to be used to verify functionality or operation of a design under test.

Abstract: Implementations can include a system to trace and identify target signals by cross-correlation to a signal pattern for a circuit, the system including a data processing system including memory and one or more processors to identify a target signal among a plurality of signals propagating through a circuit, detect one or more reference signals associated with an input to the target signal, the reference signals satisfying a threshold based on a depth associated with the target signal and the circuit, generate a cross-correlation object between the target signal and the reference signals based on a waveform of the target signal and corresponding waveforms of the reference signals, generate a metric corresponding to a cross-correlation between at least a portion of the target signal and at least a portion of the cross-correlation object, and modify, based on the metric, a control object of the circuit, the control object associated with the target signal.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at least model order reduction of the MOR-based envelope Fourier technique to the training model. A time varying system may be determined for the electronic circuit based by using at least the reduced order training model.

Abstract: A control component transmits a timing strobe and associated write data burst to a memory component, extending the write data burst to include a quantity of successive bits in excess of active edges in the timing strobe to ensure that the write data burst is sampled under worst-case timing skew conditions.

Abstract: A prefetch circuit coupled to a cache memory circuit includes a storage circuit that stores multiple virtual-to-physical address map entries. In response to receiving an indication of a miss for an access request to the cache memory circuit, the prefetch circuit generates a prefetch address and compares it to a demand address included in the access request. In response to determining that the demand address and the prefetch address are in different memory pages, the prefetch circuit generates a prefetch request using physical page information retrieved from the storage circuit.

Abstract: Methods and systems are provided for performing voltage level shifting using thin-oxide devices. The methods and systems convert an input signal associated with a first voltage domain to output signals associated with the first and second voltage domains. A first set of thin-oxide devices generate a first output signal at the high-level voltage signal when the input signal comprises a high logic level and generate the first output signal at a ground level voltage signal when the input signal comprises a low logic level. A second set of thin-oxide devices generate a second output signal at a power supply voltage level of the second voltage domain when the input signal comprises the high logic level and generate the second output signal at the second bias voltage when the input signal comprises the low logic level.

Abstract: Various embodiments provide for port generation for a circuit design based on layout connectivity information, which can be used as part of an automatic or a semi-automatic process of an electronic design automation (EDA) system. For instance, various embodiments access connectivity information for one or more networks of a circuit design, and use the connectivity information to identify pins of signal networks as positive connections for ports, and geometric shapes on references networks as candidates for negative connections for ports.

Abstract: An approach is disclosed herein for test sequence processing that is applicable to machine learning model generated test sequences as disclosed herein. The test sequence processing includes classification, grouping, and filtering. The classification is generated based on the execution of the test sequences. The grouping is performed based on information captured during the classification of the test sequences. The filtering is performed on a group by group basis to remove redundant test sequences.

Abstract: Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.

Abstract: A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.

Abstract: Methods and systems for performing post clock tree synthesis (CTS) of a clock tree include accessing, from memory, an integrated circuit design comprising a clock tree interconnecting a clock source to a plurality of clock sinks. Each clock sink has an associated current insertion delay. A mean insertion delay of the plurality of clock sinks is determined based on the associated current insertion delays of the clock sinks. A target insertion delay for the clock sinks is set based on the mean insertion delay and a target insertion delay adjustment determined for each individual clock sink. One or more clock sinks are identified that have a target insertion delay adjustment exceeding a skew threshold value. The clock tree is modified to reduce the target insertion delay adjustment, for each identified clock sink of the one or more clock sinks, to less than or equal to the skew threshold value.

Abstract: System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these ‘mapped’ connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin adjustments, correctly calculate error detection coding, and correctly read vendor identification information.

Abstract: Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second die test signal received from the second die to the external device in the elevate mode.

Abstract: A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.

Abstract: A command/address (CA) interface of a memory controller coupled to a memory component is trained (e.g., voltages and timings are adjusted to maximize signal eye opening, sample timing margins etc.) while the CA interface is operated at highest known supported controller PHY frequency. After the CA interface has been trained at highest known supported controller PHY frequency, vendor specific information (e.g., vendor ID number, clock configuration, VDDQ configuration, etc.) is read from the memory component. If the vendor specific information indicates that the CA interface may be operated at a different (e.g., higher) frequency, the memory controller reconfigures its physical interface to operate at the indicated frequency. The memory controller then re-trains its CA interface while operating the CA interface at the indicated frequency.

Abstract: The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more instances that need to be placed in the unplaced layout and the areas of the unplaced layout configured to receive the instances, wherein analyzing is based upon a row-based data structure. Embodiments may also include determining a location and an orientation for each of the one or more instances based upon the genetic algorithm and generating a placed layout based upon the determined location and orientation for each of the instances.

Abstract: Embodiments included herein are directed towards a voltage-temperature drift resistant and power efficient clock distribution circuit. Embodiments may include a current generator and a voltage generator configured to receive an input from the current generator. Embodiments may also include a regulator which may be configured to receive a reference voltage from the voltage generator as an input and to generate regulated voltage as output. The clock distribution path may operate on a regulated voltage, the regulated voltage having a value proportional to a threshold value associated with a plurality of devices included in the clock distribution path.

Abstract: This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.