Abstract: The present disclosure relates to a computer-implemented method for automatically determining pin placement associated with an electronic design. Embodiments may include receiving, using at least one processor, at least one layout associated with the electronic design and separating the at least one layout into one or more grids. Embodiments may also include extracting one or more connectivity features from the one or more grids, wherein the one or more connectivity features include instance-pin and pin information. Embodiments may also include training a machine learning model, based upon, at least in part, the one or more connectivity features and receiving the machine learning model and a test layout at a predictor engine. Embodiments may further include providing a user with a pin placement recommendation based upon, at least in part, the machine learning model and the test layout.

Abstract: Embodiments include herein are directed towards a system and method for monitoring compliance patterns. Embodiments may include a re-timer device-under-test configured to transmit a truncated compliance pattern associated with a PCIe compliance mode. Embodiments may further include a BFM monitor configured to receive the truncated compliance pattern and to identify a communication signal associated with the truncated compliance pattern. The BFM monitor may be further configured to discard at least one unexpected symbol on at least one lane associated with the communication signal and to collect compliance patterns on all lanes of the communication signal. The BFM monitor may be further configured to align one or more lane FIFOs based upon skew and to enable one or more compliance pattern checkers.

Abstract: High-speed signal propagation circuits are biased by a temperature-compensating signal-swing calibrator to yield a target output signal amplitude across process, voltage and temperature corners, avoiding the power-consumptive over-biasing conventionally employed to avoid under-amplitude conditions in slow-process, low-voltage and/or high temperature conditions.

Abstract: An approach is described for a method, product, and apparatus for a machine learning process using weight sharing within a systolic array having reduced memory bandwidth. According to some embodiments, this approach includes providing a systolic array that includes processing elements which each have some number of storage elements for storing weights. For example, the weights can be reused for different data sets by identifying/capturing a current state of the storage elements, generating a plan to transition to a target state of those storage elements, and application of the transition plan such that weights that are already stored in those storage elements can be reused and/or relocate. This lowers the bandwidth requirements for weight memory by allowing weights that have previously been read into the systolic array to be reused.

Abstract: In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.

Abstract: Aspects of the present disclosure include systems and methods for temperature adaptive voltage controlled oscillators. In one example, a voltage controlled oscillator includes a cross junction circuit electrically coupled to a temperature dependent input current, and an inductor circuit electrically coupled to the cross junction circuit. The voltage controlled oscillator additionally includes a capacitor bank circuit electrically coupled to the inductor circuit, and an input node that receives a control voltage. The voltage controlled oscillator further includes an output node configured to provide an oscillation frequency output, wherein the oscillation frequency output is controlled by the control voltage.

Abstract: Various embodiments described herein provide for a method and system for relative placement of components for a circuit layout by retrieving a data structure of a first circuit design, the data structure including a location of each component, determining a component characteristic for each component, and selecting a first group of two or more components having a shared component characteristic. Additionally, the method and system can instantiate a second circuit design and retrieve the data structure after the second circuit design is instantiated. The method and system include, for the second circuit design, calculating a first scaling factor and scaling each of the components of the first group from the first circuit design and placing the first group at a location in the second circuit design corresponding to location of the first group within the first circuit design.

Abstract: The present disclosure relates to applying genetic optimization to a routing strategy associated with an electronic design. Embodiments may include receiving pin and net information from an electronic design file and determining a minimum spanning tree for all pins associated with each net. Embodiments may include identifying pairs of connected pins and representing the pins as at least one line segment without layer information. Embodiments may include generating a crossing map based upon the line segments and assigning random layer information to each of the line segments. Embodiments may further include performing crossover and mutation operations to the line segments using hyperparameters and evaluating a fitness of the line segments. Embodiments may also include instantiating vias based upon a layer to which the line segment was assigned.

Abstract: Various embodiments provide for a cross-section parameterized cell, which can enable a user to visualize and interactively define or modify one or more wire instances and related elements/structure of a circuit design from an elevation view (or a side view).

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated and delayed multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the PLL.

Abstract: Various embodiments provide for determining redundant logic in a circuit design based on one or more enable conditions of clock gates, which can be part of electronic design automation (EDA). In particular, some embodiments use one or more enable conditions (of the clock gates) with a satisfiability solver to determine redundant logic coupled to clock circuit elements gated by the clock gates.

Abstract: Embodiments include herein are directed towards a method for electronic circuit design is provided. Embodiments may include allowing, at a graphical user interface, a user to initiate a co-design mode associated with an electronic design. Embodiments may further include allowing, at the GUI, the user to select a shape to trace connectivity from. Embodiments may also include tracing the connectivity of the shape across one or more overlaps and identifying one or more pins associated with the connectivity. Embodiments may further include determining a correct pin from an instance associated with the connectivity and displaying the connectivity at the GUI.

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic design library including a plurality of design rules. Embodiments may include generating a routing graph, based upon, at least in part, the plurality of design rules, wherein the routing graph is a virtual representation of all of the available routing space for all routing layers associated with an electronic design. Embodiments may further include dynamically updating the routing graph at a graphical user interface, based upon, at least in part, a creation of a routing segment or a via at the graphical user interface.

Abstract: Disclosed is an improved approach for efficiently implementing a three-dimensional integrated circuit (3D-IC) design with heterogeneous and/or homogeneous dies. A first die design and a second die design in a three-dimensional (3D) electronic design maybe identified, and a wrapper design may be generated for at least a block of circuit component designs in the second die design for concurrent implementation of both the first and the second die designs. Both the first and the second dies of the 3D electronic design are concurrently implemented based at least upon a floorplan that is generated with at least the wrapper design for the 3D electronic design. A first wrapper and a second wrapper may be respectively generated for the first die design and the second die design based at least in part upon a result of the concurrent implementation.

Abstract: Various embodiments provide a charge model for a cell instance for delay calculation of a circuit design that includes the cell instance, where the charge model can be part of electronic design automation (EDA) and used in timing analysis of a circuit design that includes the cell instance. The charge model generated by an embodiment can predict a charge at an input of a cell instance for an arbitrary input voltage waveform and can address (e.g., reduce or negate) a time delay impact the Miller effect has on the cell instance.

Abstract: Various embodiments provide for a continuous time linear equalizer (CTLE) that includes an active inductor, which can be included in a receiver portion of a circuit. For some embodiments, the CTLE in combination with the active inductor can implement a signal transfer function comprising at least two zeros and two poles.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, at a client electronic device, work instructions corresponding to an electronic circuit. Embodiments may further include displaying a graphical representation of the electronic circuit at a display screen associated with the client electronic device and displaying at least one instruction at the display screen, wherein displaying includes highlighting a component of the electronic circuit at the display screen.

Abstract: In some examples, a digital phase-locked loop (PLL) circuit can include a switch to provide a reference input signal having a first frequency in response to an output signal having a second frequency that is greater than the first frequency. The circuit includes a comparator to provide a series of bits based on the reference input signal and a comparator reference signal, and proportional accumulator circuits to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit. The circuit includes shift registers to shift the respective bit of the series to provide a shifted bit during the respective different time intervals, and a cancellation circuit to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit.

Abstract: Embodiments include herein are directed towards a system and method for estimating glitch power associated with an emulation process is provided. Embodiments may include accessing, using a processor, information associated with an electronic design database and generating cycle accurate waveform information at each node of a netlist based upon, at least in part, a portion of the electronic design database. Embodiments may further include generating a probability-based model for a plurality of inputs associated with the netlist and determining one or more partial glitch transitions from each probability-based model. Embodiments may also include combining the one or more partial glitch transitions with the cycle accurate waveform information to obtain a glitch power estimation.

Abstract: A method and a system for converting a variable delay in real number modeling code to cycle-driven simulation interface event for digital/mixed signal emulation is provided. The method comprises identifying a variable delay of an analog signal in real number modeling code defining an analog circuit; determining a frequency and a maximum number of cycles for a series of discrete clock cycles, wherein the variable delay corresponds to one cycle in the series of discrete clock cycles; converting the variable delay into a plurality of cycle-driven discrete events based on the series of discrete clock cycles; and generating synthesizable code based on the plurality of cycle-driven discrete events for digital mixed signal emulation. A system and a non-transitory computer readable medium to perform the above method are also provided.