Abstract: A computer may generate a record of a template associated with a schematic design corresponding to an integrated circuit design. The template may have one or more instances corresponding to one or more initial parameters associated with a chain of one or more transmission line components of the integrated circuit design. The computer may then modify content of the chain of one or more transmission line components in a circuit layout corresponding to the schematic design within the maximum range limit of the one or more initial parameters. The computer may update the one or more instances according to modified contents of the one or more transmission line components in the circuit layout.

Abstract: Systems and methods disclosed herein provide for improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”). Embodiments provide for a masking element to inject one or more faults into the ECC logic during at least one of a manufacturing test (“MFGT”) and a power-on-self-test (“POST”), wherein, based on the injected faults, it can be determined if the ECC logic contains any errors.

Abstract: Aspects of the present disclosure address systems, methods, and an improved graphical user interface (GUI) for providing interactive macro-cell placement for integrated circuit (IC) design. The method includes causing display of a GUI that includes a display of an IC floor plan comprising multiple macro-cells, The method further includes receiving a user selection of two or more macro-cells from the IC floor plan, and updating the GUI to display layout options for the two or more macro-cells in conjunction with the display of the IC floor plan. Each layout option specifies an arrangement of the two or more macro-cells. In response to a user selection of a layout option, the display of the IC floor plan is updated by modifying a placement of the two or more macro-cells in accordance with the selected layout option.

Abstract: The present disclosure relates to a method for use in the formal verification of an electronic circuit. Embodiments may include receiving, using a processor, a portion of an electronic circuit design and analyzing a syntactic structure of a string associated with the electronic circuit design. Embodiments may also include generating a parse tree, based upon, at least in part, the analysis and traversing the parse tree to identify one or more conditional nodes. Embodiments may further include generating a new node for each of the one or more conditional nodes and displaying, at a graphical user interface, a check, at least one of the one or more conditional nodes or the new node prior to performing either register-transfer-level RTL synthesis or final synthesis.

Abstract: A method for debugging a system on chip (SoC) under test, may include automatically inserting commands in a test code for testing the SoC for invoking printing of messages of data, each message of the messages including start time, end time of each executed action of a plurality of actions, the executed action to be invoked by the test code when testing the SoC, the data further including identity of a processing component of a plurality of processing components of the SoC, on which the executed action was executed; recording the data of the invoked printed messages during testing of the test code on the SoC; and displaying, via a graphical user interface, one or a plurality of graphical representations, each of said graphical representations relating to a period of activity of one of the plurality of processing components over time, based on the recorded data.

Abstract: A method for generating a validation test for testing an electronic design may include using a processor, analyzing a plurality of actions of a validated scenario to identify an executable corresponding to each of the actions and to identify one or a plurality of variables referred to by each of the actions; using a processor, identifying actions in said plurality of actions that correspond to different executables of the identified executables but refer to a same variable of said one or a plurality of variables that is to be written to or read from a shared memory assigned to the different executables; and using a processor, generating a test code for the validated scenario that includes one or a plurality of access protection commands to manage access by the identified actions that correspond to the different executables and refer to the same variable.

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations. An improved approach to perform cross-validations is provided.

Abstract: A method for identifying a physical memory(ies) associated with a logical memory(ies) in a memory design can include (a) receiving a generic netlist for the memory design, (b) generating a test mode for the memory using the generic netlist, (c) determining the logical memory(ies); (d) performing a simulation on the test mode for the logical memory(ies); and (e) identifying the physical memory(ies) by tracing chip selects for the physical memory(ies) to the logical memory(ies). The identifying the physical memory(ies) may further include identifying which chip selects are active. The identifying the physical memory(ies) can further include tracing an address and a data pin(s) for the logical memory(ies) in the simulation. The identifying the physical memory(ies) can further include determining an address and a data pin(s) for the logical memory(ies) in the simulation.

Abstract: The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include an electronic computer aided design (“CAD”) system configured to receive one or more design rules and to receive one or more manufacturing rules. The CAD system may be further configured to analyze design database objects from the electronic design with respect to the manufacturing rules. The CAD system may generate a manufacturing output file, based upon, at least in part, the analyzing. Embodiments may also include a signoff computer aided manufacturing (“CAM”) station configured to receive the manufacturing output file. The CAM station may be configured to attempt to validate the manufacturing output file.

Abstract: Various techniques implement an electronic design with physical simulations using layout artwork. The approximate behaviors of the electronic design are determined. A region in the electronic design is identified. A first three-dimensional model is identified, if pre-existing, or generated, if non-existing, for the region in the electronic design. The behaviors of the region is determined using at least physics-based techniques or methodologies that are preconditioned upon at least a portion of the approximate behaviors determined for the electronic design.

Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.

Abstract: The present disclosure relates to a computer-implemented method for use in design for manufacturing associated with a die or package. Embodiments may include providing, using a processor, an electronic design and displaying, at a graphical user interface, at least a portion of a layout associated with the electronic design. Embodiments may also include determining an expected thermal or centrifuge force manufacturing variation associated with the electronic design. Embodiments may further include allowing a user to insert, at the graphical user interface prior to signoff, a copper pillar bump or solder bump on at least a portion of the layout based upon, at least in part, the determined expected thermal or centrifuge force manufacturing variation. Embodiments may further include displaying the copper pillar bump or the solder bump on the layout at the graphical user interface.

Abstract: Disclosed are methods, systems, and articles of manufacture for binding and annotating an electronic design with a schematic driven extracted view. These techniques identify a schematic design and an extracted view of an electronic design and bind the schematic design with the extracted view. The resulting binding information concerning binding the schematic design with the extracted view is stored in a data structure. The schematic design may be annotated with extracted view information pertaining to the extracted view based at least in part upon the binding information. A response to a user action may be automatically generated based in part or in whole upon the extracted view information or the binding information.

Abstract: A method includes receiving a first list including a plurality of first curves defining a first boundary set and a second list including a plurality of second curves defining a second boundary set. The first and second curves are indicative of features in an integrated circuit based on parametric values. The method includes determining intersections between pairs of curves from the first and the second lists, assigning a node to each intersection point of a pair of curves, and determining curve sections between the intersection points for each intersected curve. The method includes determining a successor of each curve section, determining boundaries formed by the curve sections, performing the Boolean operation between the boundaries to obtain the one or more features in the integrated circuit from the two or more boundaries, and generating a layout of the integrated circuit including the features for manufacturing a mask for reproducing the features.

Abstract: The present embodiments relate to providing an overlap view of external and internal components of all instance circuit cells related to a master circuit cell in a same layout view. A layout of a circuit having a plurality of instance circuit cells of a master circuit cell is provided. Further, a graphical user interface including a user selectable option for an overlay view is provided. In addition, responsive to the selection of the overlay view, the plurality of instance circuit cells of the master circuit cell is determined. In addition, a plurality of sets of circuit elements, each set of circuit elements including external circuit elements that overlap with a corresponding instance circuit cell of the plurality of instance circuit cells is determined. Further, the plurality of sets of circuit elements overlaid on the master circuit cell is displayed on the layout view.

Abstract: A delay line can include a number of delay elements connected in series, each selected to impart an overall delay to an input signal. The delay line can include delay selection logic to select a subset of the delay elements to delay the input signal. The delay line can include delay element enable logic to enable the selected subset of the delay elements to delay the input signal. Further, the remaining delay elements can be disabled from contributing any delay to the input signal, and a respective periodic signal can be provided to at least one of the remaining delay elements to cause the at least one remaining delay elements to output an output signal that is a function of the respective periodic signal and that has a frequency less than that of the input signal. This configuration can reduce asymmetric aging effects on the delay line.

Abstract: The present embodiments relate to buffering signals between disjointed power domains with similar power profiles in an integrated circuit. According to some aspects, embodiments relate to a method in which an electronic design automation (EDA) tool displays a schematic including a plurality of first power domains having a first power profile and a plurality of second power domains having a second power profile. The EDA tool generates graph including a plurality of points and a plurality of edges connecting the points, where the points are located on the plurality of second power domains. The EDA tool selects one route from a plurality of routes from a start node on the graph to an end node on the graph and determines a number of buffers located on the route based on associated distance values and a design violation values.

Abstract: The present disclosure relates to a system and method for use in an electronic design environment. Embodiments may include receiving, using at least one processor, an electronic design and generating a unique name for each hardware state element associated with the electronic design. Embodiments may further include generating a unique name for each software state element associated with the electronic design. Embodiments may also include combining a plurality of unique names into an arbitrary expression, wherein the plurality of unique names includes at least one software state unique name and at least one hardware state unique name. Embodiments may further include evaluating the arbitrary expression at one or more discrete time points. Embodiments may also include recording an evaluated expression in an electronic design database.

Abstract: An approach is described for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification tools. According to some embodiments, the approach includes identification of a waiver of an error or warning, registration of one or more condition sets for waiver of an error or warning, waiver of multiple errors or warnings that match the registered one or more condition sets, and further comprise any or all of the following: receiving or retrieving a circuit design, analyzing the circuit design to identify errors and warnings, and displaying identified errors and warnings where errors and warnings matching a registered condition set are waived. This approach provides for a 1-to-many relationship between identification of a waiver and application of waivers.

Abstract: Devices, methods, computer readable media, and other embodiments are described for design and verification of safety critical electronic systems. Some embodiments integrate functional safety (FS) data with circuit design data for use in electronic design automation (EDA) operations. One embodiment involves a device accessing FS and circuit design data; automatically analyzing register transfer level (RTL) design data using the FS data to perform one or more FS quality checks; and placing and routing the circuit design using the RTL design data and the set of FS data to perform FS-aware placement and routing. In some embodiments, failure modes and associated safety mechanisms to improve safety metrics associated with failure modes are automatically added to the circuit design during EDA operations. In other embodiments, additional FS-aware operations are performed. In some embodiments, the FS data is structured as a single Unified Safety Format (USF) file.