Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising an irregular sink arrangement. Different grid templates may be identified for assisting with balanced routings at different levels of a routing tree to connect the sinks of the circuit design. As part of such operations, costs for different routings using the different grid templates are calculated and compared. A lowest cost routing for each grid template are identified. These costs are normalized across different grid templates, and a lowest cost routing across all grid templates is selected. In various embodiments, various costs values based on sink pairing, isolated sinks, and node position for a next level of a routing tree are considered.

Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design awareness. Embodiments may include providing, using a processor, an electronic design having a package layout and a die layout associated therewith. Embodiments may also include displaying at a graphical user interface, the package layout and allowing, at the graphical user interface, a user to edit the package layout. Embodiments may further include determining, using the processor, an impact of the edit on the die layout and in response to the edit, mirroring the edit at the die layout.

Abstract: Various techniques implement an electronic design with hybrid analysis techniques. An activity map is identified or generated for an electronic design. The electronic design is reduced into a reduced electronic design at least by applying a plurality of reduction processes to different portions of the electronic design based in part or in whole upon the activity map. Transient behaviors of the electronic design may be determined or predicted at least by performing one or more transient analyses on a representation of the electronic design with a simulation start point based in part or in whole upon the activity map. The electronic design may then be implemented for manufacturing at least by modifying or correcting the electronic design based at least in part upon the transient behaviors.

Abstract: The present disclosure relates to a computer-implemented method for parasitic extraction. The method may include providing, using one or more processors, an electronic design having IP and/or metal fill content associated therewith. The method may further include identifying at least one layer associated with the content to be modeled and identifying at least one layer associated with the content to be ignored. The method may also include discarding one or more shapes associated with the at least one layer associated with the content to be modeled and replacing each discarded shape with an alternative shape. The method may further include modeling the electronic design including the alternative shape, wherein modeling is electrically aware in a horizontal and a vertical direction.

Abstract: The present disclosure relates to a method for electronic design. Embodiments may include receiving, using a processor, an electronic design and performing formal verification upon at least a portion of the electronic design for a specific problem statement. Embodiments may further include generating a plurality of traces associated with the formal verification satisfying the specific problem statement and displaying, at a graphical user interface, an option to select at least one of the plurality of traces for display at the graphical user interface while the formal verification is performed.

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations.

Abstract: Embodiments included herein may be used for characterizing and analyzing an electronic system design including a parallel interface. Embodiments may include identifying an electronic design including a design of a parallel interface. Embodiments may also include determining a single circuit representation including the design of the parallel interface from the electronic design. Embodiments may further include analyzing the single circuit representation at a channel analysis module stored at least partially in memory and functioning in tandem with a computing system to determine waveform responses of the parallel interface and a remainder of the single circuit representation by using channel analysis techniques. The channel analysis techniques may be based upon a data channel simulation and a strobe channel simulation.

Abstract: The present disclosure relates to a system and method for algorithmic modeling interface (“AMI”) model development. Embodiments may include enabling a selection from a plurality of templates associated with an advanced equalization algorithm at a graphical user interface. Embodiments may further include receiving a selection of at least one of the plurality of templates at the graphical user interface and displaying a selected template at the graphical user interface. Embodiments may also include allowing a user to edit one or more parameters associated with the selected template at the graphical user interface and generating an algorithmic modeling interface (“AMI”) model based upon, at least in part, the selected template and the one or more parameters.

Abstract: Aspects of the present disclosure address systems and methods for dynamically adjusting skew windows during clock tree synthesis (CTS). A method may include identifying a pin insertion delay (PID) assigned to a clock sink in a set of clock sinks of a buffer tree in an integrated circuit design. The method further includes determining a skew window for the clock sink based on a skew target and adjusting the skew window based on identifying the PID assigned to the clock sink. The skew window is adjusted based on a skew adjustment parameter. The method further includes building a clock tree based on the buffer tree and the adjusted skew window. The building of the clock tree comprises tuning a clock path delay of the clock sink according to the adjusted skew window. A layout instance may be generated for the IC design based in part on the clock tree.

Abstract: The present disclosure relates to a system and method for linking GUI plug-ins with multiple data providers. Embodiments may include allowing, via one or more computing devices, at least one data provider access to a data abstraction layer. Embodiments may further include allowing at least one GUI plug-in access to the data abstraction layer and receiving, at the data abstraction layer, a query from the at least one GUI plug-in. In response to the query, embodiments may include retrieving one or more data sets from the at least one data provider and aggregating a subset of the one or more data sets from the at least one data provider. Embodiments may further include providing the subset of the one or more data sets to the at least one GUI plug-in.

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include providing, using at least one processor, an electronic design and performing linting analysis using structural and formal methods of at least a portion of the electronic design. Embodiments may also include identifying a plurality of failures from the formal verification and identifying one or more of the plurality of failures as having a similar root cause. Embodiments may include grouping the one or more of the plurality of failures together, wherein grouping is based upon, at least in part, a check type.

Abstract: A method for processing verification tests for testing a design under test (DUT), may include receiving from a user a start time message and an end time message for each action of actions in a verification test in a target code form, to be printed into a log file of an execution of the test, so as to list chronologically the start time and end time of each of the actions in the log file. The method may also include executing the verification test to obtain the log file with the start time and end time messages and, using a processor, analyzing the log file to construct a graph representation of the validation test, based on the printed start and end times of the actions of the test.

Abstract: Disclosed herein are embodiments of systems, methods, and products to automatically and intelligently generate a test bench to test an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) design. A computer may receive netlist of the IC design forming a device under test (DUT). From the DUT, the computer may extract and/or calculate one or more parameters. Based on the one or more parameters, the computer may generate a test bench comprising a resistance inductance capacitance (RLC) circuit to provide ESD stimulus to the DUT. The ESD stimulus and therefore the test bench may be based on a human body model (HBD) or a charged device model (CDM). In case of the CDM, the computer may allow a circuit designer to select or deselect package parameters for testing the ESD protection circuit.

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include displaying, at a graphical user interface, an electronic circuit design topology environment and allowing a user to select, create, or modify an entirely single pin topology, an entirely multi-pin topology, or a combination of a single pin topology and a multi-pin topology for one or more portions of the electronic circuit design topology environment. Embodiments may also include receiving a selection of a designated portion of the electronic circuit design topology environment and generating, at the graphical user interface, a first, pin-adjustable symbol in accordance with the selected topology at the designated portion.

Abstract: A method for combining verification data may include using a processor, obtaining verification data and a verification model from each of a plurality of verification engines relating to different verification methods, the verification data relating to a plurality of verification tests that were conducted on a design under test (DUT) using the plurality of verification engines; using a processor, merging the verification models obtained from the plurality of verification engines into a merged verification model; using a processor, calculating a combined verification metric grade for a plurality of verification entities in the merged verification model using verification metric grades for each of the plurality of verification entities calculated from the verification data obtained from the plurality of engines and applying a combined verification metric grade rule; and outputting the combined verification metric grade via an output device.

Abstract: The present disclosure relates to modeling the transient current of a partially simulated hierarchical gate-level electronic design. Embodiments may include providing a partially simulated hierarchical gate-level electronic design, wherein the design includes a design hierarchy having one or more leaf blocks associated therewith. Embodiments may also include identifying activity of sequential elements of the leaf blocks using simulation vectors, wherein the activity is used to estimate an amount of current associated with the sequential elements. Embodiments may further include computing an adaptive activity of a parent block of the leaf blocks, wherein the adaptive activity of the parent block corresponds to a weighted average of known activity of leaf blocks. Embodiments may also include generating an adaptive activity of a top block of the leaf blocks based upon the adaptive activity of the parent block and performing a mixed-mode simulation based upon the adaptive activity of the top block.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include providing an electronic design having a plurality of geometric elements and generating a non-design element. Embodiments may further include associating the non-design element with one of the plurality of geometric elements and storing the non-design element with the one of the plurality of geometric elements. Embodiments may also include displaying, at a graphical user interface, the non-design element upon selection of the geometric element.

Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.

Abstract: A method for reconstructing a graph representation of a previously executed verification test, may include obtaining a truncated chronicle of start time and end time messages of actions of the verification test that were logged during execution of the verification test on a design under test (DUT); using a processor, parsing and analyzing the start time and the end time messages to determine an order of the actions; using a processor, determining an order of other actions of said verification test, based on a graph representation of a verified scenario from which the verification test was generated; and reconstructing the graph representation of the verification test based on the determined order of the actions and order of the other actions.

Abstract: Various embodiments provide for a memory controller capable of detecting an error on addressing (address error or address fault) of memory commands for a memory device implementing an inline storage configuration of primary data with associated error checking data. According to some embodiments, the memory controller indicates that an address error of a particular memory command has occurred (or likely occurred) by detecting when a plurality of data errors is produced by a plurality of error checks performed on primary data resulting from the particular memory command. Various embodiments described herein allow both single-bit error detection and correction, and address protection to exist in a memory solution implementing an inline error checking data storage configuration, such as inline ECC storage configuration.