Abstract: Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points, and the initial movement is expanded to consider additional placement options for the clock gate based on the data path connection points.

Abstract: Disclosed are methods, systems, and articles of manufacture for probing a multi-fabric electronic design that spans across multiple design fabrics. These techniques identify a single layout editor, a first electronic design in a first design fabric, and a second electronic design in a second design fabric. An input for probing a circuit component in the first electronic design may further be identified at a user interface of a computing system. The circuit component being probed is connected to an instance of the second electronic design. In response to the input, one or more co-design modules render a representation of the first layout with emphasized circuit components in the first design fabric and the second design fabric, wherein the one or more co-design modules are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system.

Abstract: Disclosed are methods, systems, and articles of manufacture for reducing interferences and disturbances in a multi-fabric electronic design. These techniques identify connectivity for an electronic design that includes design data in multiple design fabrics. One or more interference modules are executed to detect a loop in the electronic design with at least the connectivity. These techniques further execute the one or more interference reduction modules to determine at least one critical circuit component upon which the loop exerts a negative impact. One or more remedial actions are then triggered to reduce or eliminate the negative impact on the critical circuit component design.

Abstract: According to certain aspects, the present embodiments are directed generally to data communication systems, and more particularly to generating multi-phase clocks in a SerDes system. Embodiments provide SerDes components and methods that are capable of generating multiple different sampling frequencies for parallelizing serial data from a single high speed clock. These and other embodiments can be implemented with circuits that are relatively small and low-power as compared to conventional approaches.

Abstract: Aspects of the present disclosure address a slew rate controlled driver. The slew rate controlled driver includes an amplifier with a capacitive feedback loop and a current generator capable of producing a current that is proportional to on-chip capacitance. The current generator is implemented using a switched capacitor and supplies the driver with a current that is proportional to the capacitance of the switched capacitor. By supplying the driver with current that is proportional to the capacitance of the switched capacitor, the slope of the output signal of the driver is proportional to the ratio of the switched capacitance and a capacitance of the driver's capacitive feedback loop.

Abstract: Various embodiments describe performing a transient simulation of circuits that have mutual inductors. In particular, some embodiments perform a transient simulation on a circuit model by removing and approximating the effects of one or more entries of a matrix in the circuit model, where the matrix relates to inductors or mutual inductors of the circuit. In doing so, such embodiments can render the matrix more sparse than before which, in turn, can reduce the time spent during the transient simulation to solve equations of the circuit model.

Abstract: A method includes finding, for a discretized curve comprising multiple segments, first and second segments that are closer than a threshold. The method includes determining an intersection point of the first segment and the second segment, the intersection point associated with a first parameter value for the first segment and a second parameter value for the second segment, determining an error value as a distance between a first point in the parametric curve corresponding to the first parameter value and a second point in the parametric curve corresponding to the second parameter value, and selecting the intersection point when the error value is smaller than a precision tolerance. The method includes transforming the discretized curve by removing at least a segment between the first segment and the second segment, and providing the discretized curve to manufacture a mask for reproducing the feature in the integrated circuit.

Abstract: Aspects of the present disclosure address improved systems and methods for layer assignment to improve timing in integrated circuit (IC) designs. An initial placement layout of a net of an IC design is accessed. A plurality of buffer insertion candidates is generated using multiple candidate buffer insertion points and multiple layer assignments from among multiple layers of the IC design. Timing characteristics of each buffer insertion candidate are determined, and timing improvements provided by each buffer insertion candidate are determined based on respective timing characteristics. A buffer insertion candidate is selected from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate. A layout instance for the IC is generated based in part on the selected buffer insertion candidate.

Abstract: Disclosed herein are systems and methods of compiling resources of a programmable emulation system to execute an emulation process, to emulate a logic system, such as an application-specific integrated circuit (ASIC), currently being tested and prototyped, and then revising, transforming, and moving the compiled instructions sets to inexpensively, quickly, and dynamically adapt to unavailable resources, which may be due to previously allocation to a different emulation job, or for fault tolerance. Relocation of the resources that will execute the emulation job (i.e., “footprint”) may refer to the remapping of a compiled footprint to a revised set of resources, defining a revised footprint. Fault tolerance may refer to support for working around faulty hardware components of the emulation system.

Abstract: Electronic design automation systems, methods, and media are presented for slack scheduling. Some embodiments analyzing slack values at the input and output of a circuit element across multiple views. A skew value is then selected which maximizes the slack at the input and output of the circuit element across all views. In some embodiments, this selection operation is streamlined by first identifying skew ranges that preserve a local worst negative slack, and the selected skew value to maximize the slacks is chosen from the identified skew ranges, in order to limit the computational resources in identifying the skew which maximizes the minimum slack value. An updated circuit design and associated circuitry may then be generated.

Abstract: Various embodiments provide for assigning a clock pin to a clock tap within a circuit design based on connectivity between circuit devices of the circuit design. For some embodiments, an initial clock tap assignment, between a clock tap of a circuit design and a clock pin of the circuit design, is accessed as input, and a modified clock tap assignment (between the clock tap and another clock pin of the circuit design) can be generated based on one or more of the following considerations: a clock tap assignment should try to assign clock pins of connected circuit devices to the same clock tap; a clock tap assignment should try to assign clock pins of connected circuit devices having the critical timing problems; a clock tap assignment should try to assign clock pins of connected circuit devices to clock taps with longer common path length.

Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design includes selecting by a processor a plurality of cutpoints in the two representations of the electronic design, rendering the two representations of the electronic design abstracted; executing by the processor an assume-guarantee (AG) proof on the two abstracted representations of the electronic design; identifying by the processor a failed assertion indicating non-equivalence of a signal pair relating to one of the cutpoints; and performing by the processor a simulation on the two representations of the electronic design by successively inputting input stimuli of a trace corresponding to the failed assertion in a sequential order in which the input stimuli appear in the trace at inputs of the two representations of the electronic design to identify whether there is one or a plurality of additional non-equivalent signal pairs relating to other cutpoints of said plurality of cutpoints.

Abstract: Devices, methods, non-transitory computer readable media, and other embodiments are described for automatic gate-level functional safety (FS) analysis and associated circuit design operations. One embodiment involves accessing register transfer level (RTL) design data, and accessing a set of FS data associated with an initial circuit design describing one or more failure modes associated with a plurality of circuit elements, an associated FS design criterion for each failure mode of the one or more failure modes, and one or more associations between the plurality of circuit elements and the one or more failure modes. The embodiment then involves generating a gate-level netlist using the RTL design data, mapping the one or more associations between the plurality of circuit elements from the RTL design data and the one or more failure modes to the gate-level netlist, and generating an updated set of FS data using the mapping of the one or more associations to the gate-level netlist.

Abstract: Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

Abstract: According to an aspect of this disclosure, a computer-implemented method of offsetting boundary curves includes providing a plurality of inputs for an identified boundary set, developing an offset distance, and creating an offset boundary curve for each boundary. The method of offsetting boundary curves further includes determining intersection points of each of the offset boundary curves, assigning a node to each of the intersection points, and determining sections between intersection points for each offset curve. Still further this method includes determining a minimum distance between sections, wherein when the sections are nearer one another than the minimum distance the sections are determined to belong to the same node and combining the offset boundary curves to define a set of offset boundary curves.

Abstract: A method includes programming an FPGA based controller of a master blade with a power scheme. The master blade receives a first power management signal from the master blade and slave blades. The master blade transmits a second power management signal to itself and to the slave blades responsive to the first power management signal. The master blade receives a third power management signal from itself and the slave blades. The power scheme controls an order and delay in which the second power management signal is transmitted to the first master blade and the slave blades. The power scheme controls an order and delay in which the third power management signal is received from the master blade and the slave blades. The system can be expanded by connecting the master blades to a grand master blade and multiple grand master blades to a great grand master blade.

Abstract: Circuits, methods and systems that are to be used for dynamically modulating a high frequency bit duration of data based on a status of one or more previous transmitted bits. One circuit comprises a first data path comprising a first input, a first buffer, and a first output connected to a first multiplexer data input. The circuit further comprises a second data path comprising a second input, a second buffer, a phase interpolator, and a second output coupled to a second multiplexer data input. The circuit further comprises a multiplexer having at least two data inputs, at least one control input, and a common output coupled to a transmitter signal line and wherein the at least one control input is operatively coupled to a generated control signal that is based on the status of one or more previous transmitted bits.

Abstract: Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree. The approach captures users' design intent about the topology, and the routing system adhere to that topology intent throughout the layout process.

Abstract: A method for a combined formal static analysis of a design code, the method comprising using a lint checker performing Lint checks to identify a suspected violation in the design code; using a formal static analyzer, performing formal checks to identify a suspected property that corresponds to the suspected violation; applying a formal proof technique to determine whether the suspected property is proven or disproved; and if the suspected property is disproved, issuing an alert.