Abstract: The present disclosure relates to a system and method for linking GUI plug-ins with multiple data providers. Embodiments may include allowing, via one or more computing devices, at least one data provider access to a data abstraction layer. Embodiments may further include allowing at least one GUI plug-in access to the data abstraction layer and receiving, at the data abstraction layer, a query from the at least one GUI plug-in. In response to the query, embodiments may include retrieving one or more data sets from the at least one data provider and aggregating a subset of the one or more data sets from the at least one data provider. Embodiments may further include providing the subset of the one or more data sets to the at least one GUI plug-in.

Abstract: A method for processing verification tests for testing a design under test (DUT), may include receiving from a user a start time message and an end time message for each action of actions in a verification test in a target code form, to be printed into a log file of an execution of the test, so as to list chronologically the start time and end time of each of the actions in the log file. The method may also include executing the verification test to obtain the log file with the start time and end time messages and, using a processor, analyzing the log file to construct a graph representation of the validation test, based on the printed start and end times of the actions of the test.

Abstract: Disclosed herein are embodiments of systems, methods, and products to automatically and intelligently generate a test bench to test an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) design. A computer may receive netlist of the IC design forming a device under test (DUT). From the DUT, the computer may extract and/or calculate one or more parameters. Based on the one or more parameters, the computer may generate a test bench comprising a resistance inductance capacitance (RLC) circuit to provide ESD stimulus to the DUT. The ESD stimulus and therefore the test bench may be based on a human body model (HBD) or a charged device model (CDM). In case of the CDM, the computer may allow a circuit designer to select or deselect package parameters for testing the ESD protection circuit.

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.

Abstract: A method for combining verification data may include using a processor, obtaining verification data and a verification model from each of a plurality of verification engines relating to different verification methods, the verification data relating to a plurality of verification tests that were conducted on a design under test (DUT) using the plurality of verification engines; using a processor, merging the verification models obtained from the plurality of verification engines into a merged verification model; using a processor, calculating a combined verification metric grade for a plurality of verification entities in the merged verification model using verification metric grades for each of the plurality of verification entities calculated from the verification data obtained from the plurality of engines and applying a combined verification metric grade rule; and outputting the combined verification metric grade via an output device.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include providing an electronic design having a plurality of geometric elements and generating a non-design element. Embodiments may further include associating the non-design element with one of the plurality of geometric elements and storing the non-design element with the one of the plurality of geometric elements. Embodiments may also include displaying, at a graphical user interface, the non-design element upon selection of the geometric element.

Abstract: The present disclosure relates to modeling the transient current of a partially simulated hierarchical gate-level electronic design. Embodiments may include providing a partially simulated hierarchical gate-level electronic design, wherein the design includes a design hierarchy having one or more leaf blocks associated therewith. Embodiments may also include identifying activity of sequential elements of the leaf blocks using simulation vectors, wherein the activity is used to estimate an amount of current associated with the sequential elements. Embodiments may further include computing an adaptive activity of a parent block of the leaf blocks, wherein the adaptive activity of the parent block corresponds to a weighted average of known activity of leaf blocks. Embodiments may also include generating an adaptive activity of a top block of the leaf blocks based upon the adaptive activity of the parent block and performing a mixed-mode simulation based upon the adaptive activity of the top block.

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include displaying, at a graphical user interface, an electronic circuit design topology environment and allowing a user to select, create, or modify an entirely single pin topology, an entirely multi-pin topology, or a combination of a single pin topology and a multi-pin topology for one or more portions of the electronic circuit design topology environment. Embodiments may also include receiving a selection of a designated portion of the electronic circuit design topology environment and generating, at the graphical user interface, a first, pin-adjustable symbol in accordance with the selected topology at the designated portion.

Abstract: Various embodiments provide for a memory controller capable of detecting an error on addressing (address error or address fault) of memory commands for a memory device implementing an inline storage configuration of primary data with associated error checking data. According to some embodiments, the memory controller indicates that an address error of a particular memory command has occurred (or likely occurred) by detecting when a plurality of data errors is produced by a plurality of error checks performed on primary data resulting from the particular memory command. Various embodiments described herein allow both single-bit error detection and correction, and address protection to exist in a memory solution implementing an inline error checking data storage configuration, such as inline ECC storage configuration.

Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.

Abstract: A method for reconstructing a graph representation of a previously executed verification test, may include obtaining a truncated chronicle of start time and end time messages of actions of the verification test that were logged during execution of the verification test on a design under test (DUT); using a processor, parsing and analyzing the start time and the end time messages to determine an order of the actions; using a processor, determining an order of other actions of said verification test, based on a graph representation of a verified scenario from which the verification test was generated; and reconstructing the graph representation of the verification test based on the determined order of the actions and order of the other actions.

Abstract: A system and method for an interactive circuit layout design that provides spatially adaptive overlay indicative of parametric properties. A physical layout of an electrical circuit product is rendered on a display. At least one net of the physical layout is delineated into a plurality of net segments each having at least one physical property parametrically specified in a value therefor. For each net segment, a corresponding segment indicator is selectively rendered on the display, adaptively positioned and spatially mapped to the net segment corresponding thereto as a symbolic surrogate for the corresponding net segment within the physical layout. Selection of a net segment actuates determination of a behavior of the electrical circuit product during an operation consistent with an electrical response of the corresponding net segment. Editing of a net of the physical layout delineates a plurality of updated net segments for the edited net exclusive of other nets.

Abstract: Implementations described herein relate to circuits and techniques increasing transmitter output speed. In some implementations, a circuit is described using a pull-up data path comprising a first flying capacitor, a first buffer, a thin-oxide PMOS device, and a thick-oxide PMOS device, a pull-down data path comprising a second flying capacitor, a second buffer, a thin-oxide NMOS device, and a thick-oxide NMOS device, wherein the pull-up data path and the pull-down data path are operatively connected to a core data output signal line.

Abstract: The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for generating electronic design element symbols for electronic circuit design tool libraries and designs in any desired format. In embodiments, such electronic design element symbols can be generated from a datasheet or any other image using image processing, graphical shape and text recognition techniques. Embodiments use step by step processing to extract feature vectors from a symbol/design image, apply text and graphical shapes recognition using models, apply techniques for data association and write the final output for targeted systems. These and other embodiments can feed back the output data for further refinement of the recognition models.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.

Abstract: In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to techniques for analyzing a design for potential ESD instance failures. Embodiments allow for efficiently determining a potential ESD violation or non-violation status for a large number of instances, such as all the instances in a full chip design, by performing effective resistance analyses between all the instances and all the bumps and ESD protection devices in the design. These and other embodiments further allow for more detailed effective resistance analyses to be performed for potential failing instances.

Abstract: Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during ATPG in order to enable clock gates in certain regions of the two-dimensional grid.

Abstract: Described is an improved approach to implement EM analysis, where the analysis can be performed early stages of the design process. Tree-routing is implemented using a structural routing solution, where an automatic routing mechanism is performed to generate a complete routing tree. That routing tree is then used to perform topology-driven EM analysis at various stages of the design process.

Abstract: Disclosed is an improved approach to implement training for memory technologies, where a data valid window is re-determined using boundary information for a new data valid window. The information obtained for the new location of the first edge is used to minimize the computational resources required to identify the location of the second edge. This greatly improves the efficiency of the process to perform the re-training.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.