Abstract: Aspects of the present disclosure address improved systems and methods for layer assignment to improve timing in integrated circuit (IC) designs. An initial placement layout of a net of an IC design is accessed. A plurality of buffer insertion candidates is generated using multiple candidate buffer insertion points and multiple layer assignments from among multiple layers of the IC design. Timing characteristics of each buffer insertion candidate are determined, and timing improvements provided by each buffer insertion candidate are determined based on respective timing characteristics. A buffer insertion candidate is selected from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate. A layout instance for the IC is generated based in part on the selected buffer insertion candidate.

Abstract: A method includes finding, for a discretized curve comprising multiple segments, first and second segments that are closer than a threshold. The method includes determining an intersection point of the first segment and the second segment, the intersection point associated with a first parameter value for the first segment and a second parameter value for the second segment, determining an error value as a distance between a first point in the parametric curve corresponding to the first parameter value and a second point in the parametric curve corresponding to the second parameter value, and selecting the intersection point when the error value is smaller than a precision tolerance. The method includes transforming the discretized curve by removing at least a segment between the first segment and the second segment, and providing the discretized curve to manufacture a mask for reproducing the feature in the integrated circuit.

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

Abstract: Systems and methods for creating learning-based personalized user interfaces for software applications are described. Exemplary embodiments provide for collecting usage data and applying machine learning techniques to identify and prioritize certain commands and options in the personalized user interface. The usage data can include Usage patterns, usage sequences, and the usage of certain commands and options in connection with, or following, certain other commands and options may also be identified, and the personalization-based prioritization can include, for example, the contents, position, and quantities of the commands and options within the interface.

Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design includes selecting by a processor a plurality of cutpoints in the two representations of the electronic design, rendering the two representations of the electronic design abstracted; executing by the processor an assume-guarantee (AG) proof on the two abstracted representations of the electronic design; identifying by the processor a failed assertion indicating non-equivalence of a signal pair relating to one of the cutpoints; and performing by the processor a simulation on the two representations of the electronic design by successively inputting input stimuli of a trace corresponding to the failed assertion in a sequential order in which the input stimuli appear in the trace at inputs of the two representations of the electronic design to identify whether there is one or a plurality of additional non-equivalent signal pairs relating to other cutpoints of said plurality of cutpoints.

Abstract: A method includes programming an FPGA based controller of a master blade with a power scheme. The master blade receives a first power management signal from the master blade and slave blades. The master blade transmits a second power management signal to itself and to the slave blades responsive to the first power management signal. The master blade receives a third power management signal from itself and the slave blades. The power scheme controls an order and delay in which the second power management signal is transmitted to the first master blade and the slave blades. The power scheme controls an order and delay in which the third power management signal is received from the master blade and the slave blades. The system can be expanded by connecting the master blades to a grand master blade and multiple grand master blades to a great grand master blade.

Abstract: Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.

Abstract: According to an aspect of this disclosure, a computer-implemented method of offsetting boundary curves includes providing a plurality of inputs for an identified boundary set, developing an offset distance, and creating an offset boundary curve for each boundary. The method of offsetting boundary curves further includes determining intersection points of each of the offset boundary curves, assigning a node to each of the intersection points, and determining sections between intersection points for each offset curve. Still further this method includes determining a minimum distance between sections, wherein when the sections are nearer one another than the minimum distance the sections are determined to belong to the same node and combining the offset boundary curves to define a set of offset boundary curves.

Abstract: Devices, methods, non-transitory computer readable media, and other embodiments are described for automatic gate-level functional safety (FS) analysis and associated circuit design operations. One embodiment involves accessing register transfer level (RTL) design data, and accessing a set of FS data associated with an initial circuit design describing one or more failure modes associated with a plurality of circuit elements, an associated FS design criterion for each failure mode of the one or more failure modes, and one or more associations between the plurality of circuit elements and the one or more failure modes. The embodiment then involves generating a gate-level netlist using the RTL design data, mapping the one or more associations between the plurality of circuit elements from the RTL design data and the one or more failure modes to the gate-level netlist, and generating an updated set of FS data using the mapping of the one or more associations to the gate-level netlist.

Abstract: Circuits, methods and systems that are to be used for dynamically modulating a high frequency bit duration of data based on a status of one or more previous transmitted bits. One circuit comprises a first data path comprising a first input, a first buffer, and a first output connected to a first multiplexer data input. The circuit further comprises a second data path comprising a second input, a second buffer, a phase interpolator, and a second output coupled to a second multiplexer data input. The circuit further comprises a multiplexer having at least two data inputs, at least one control input, and a common output coupled to a transmitter signal line and wherein the at least one control input is operatively coupled to a generated control signal that is based on the status of one or more previous transmitted bits.

Abstract: Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree. The approach captures users' design intent about the topology, and the routing system adhere to that topology intent throughout the layout process.

Abstract: According to an embodiment, a system and method are provided for supporting interactive debugging of embedded software (ESW) on a simulation platform. A processor model within the simulated system will support a register and memory tracing sub-module. Simulator and emulator breakpoints will be used with the modeled objects within the tracing sub-module. For example, a simulator breakpoint may be set for the task or function that buffers the trace information so it can be written to a file. A database of register and memory values which represent the complete history of register and memory value changes during a simulation can be created from trace information and can be accessed to non-intrusively obtain any processor register or memory value during simulation. The processor register and memory values of the database can also be accessed to symbolically show the behavior of ESW concurrently with hardware behavior in the simulation.

Abstract: A method for a combined formal static analysis of a design code, the method comprising using a lint checker performing Lint checks to identify a suspected violation in the design code; using a formal static analyzer, performing formal checks to identify a suspected property that corresponds to the suspected violation; applying a formal proof technique to determine whether the suspected property is proven or disproved; and if the suspected property is disproved, issuing an alert.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify connectivity of an electronic design that includes an embedded circuit, and the embedded circuit is located between a first actual layer and a second actual layer of the electronic design. The electronic design is then transformed, but one or more embedded circuit modules, into a transformed electronic design at least by generating one or more artificial interconnects between the embedded circuit and a plurality of metal patches. The connectivity may be re-established based at least in part upon the plurality of metal patches. The electronic design may then be implemented based at least in part upon predicted behaviors of the transformed electronic design.

Abstract: Electronic design automation systems, methods, and media are presented for a waveform propagation timing model for use with circuit designs and electronic design automation (EDA). One embodiment involves generating a gate output waveform for a circuit element using a driver input signal waveform and then generating a circuit element output waveform using the gate output waveform and an N-pole model of an interconnect with the first circuit element using moment matching. Timing values are then determined from the circuit element output waveform, such as delay and slew values. This waveform may then be propagated through the circuit, and an updated design generated using the timing values estimated from the modeled waveforms.

Abstract: Various embodiments provide for partial selection-based (e.g., cut-based) model extraction from a layout of a circuit design, which can be used to generate a schematic extracted view for the circuit design and to back annotate a schematic of the circuit design. For some embodiments, the selection comprises a cut of a layout of a circuit design, where the cut may be defined (e.g., inputted) by a user through a graphical user interface that is presenting the layout.

Abstract: Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.

Abstract: In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the plurality of EDA programs based on a respective one of the changes in the RTL operations of the RTL design.

Abstract: Systems, methods, media, and other such embodiments described herein relate to critical area analysis (CAA) operations as part of electronic design automation (EDA). One embodiment involves accessing a circuit design having a first layer (which may be a composite layer), sampling the first layer, and performing an initial CAA using the sampled portions of the layer with a set of predetermined defect sizes. The initial CAA is used to automatically generate a model which can be used to accurately select input parameters (e.g., selected defect sizes) for a full analysis. A CAA characteristic is then calculated for the first layer using the input parameters. In various embodiments, different sampling percentages and criteria for selecting input parameters can be used to reduce the computing resources to compute a CAA characteristic, such as theta-bar, while limiting error to a threshold amount (e.g. less than one percent).

Abstract: Aspects of the present disclosure address systems and methods for shortening clock-tree wirelength based on target offsets in connected routes. A clock tree comprising routes that interconnect a plurality of clock-tree instances is accessed from memory. A clock-tree instance is selected for evaluation. A baseline power consumption measurement corresponding to a sub-tree of the clock-tree instance with the clock-tree instance at a first size is determined. An alternative power consumption measurement corresponding to the sub-tree of the clock-tree instance with the clock-tree instance at a second size is determined. Based on determining that the baseline power consumption measurement is less than the alternative power consumption measurement, the clock-tree instance is resized according to the second size.