Abstract: Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may achieve this by identifying, after post-route-optimization, critical clock-tap-to-clock-device assignments based on timing analysis results (e.g., from AOCV/CPPR timing analysis) and feeding back those critical clock-tap-to-clock-device assignments to a process performing new clock tap assignments.

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of clock routing trees. One embodiment involves accessing a circuit design and a clock tree hierarchy input indicating a nested list of partition or sink groups, each group of the nested list of groups comprising one or more clock tree elements of a plurality of clock tree elements from the circuit design. A routing topology associated with a source and a plurality of sinks are determined based on an ordering within the nested list of partition groups. These routing directions are used in synthesizing a clock tree for the circuit design. In additional embodiments, the clock tree hierarchy input provides clustering information, port placement for connections between partition groups of the clock tree, and parameters describing limitations or criteria for individual partition groups.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing legal routing tracks across virtual hierarchies and legal placement patterns. These techniques identify at least a layout or a portion thereof and determine one or more legal sets of routing tracks for the layout or the portion. One or more figure groups are identified or generated at a first virtual hierarchy, and the one or more first figure groups inherit respective portions of the one or more legal sets of routing tracks. A plurality of legal devices are identified in a layout or a portion thereof, and a figure group is generated at least by determining a boundary for the figure group and enclosing the plurality of layout devices within the boundary. These techniques may modify a placement row without disturbing compliance of one or more design rules with which the legal device pattern complies when generated.

Abstract: According to certain general aspects, the present embodiments allow register files and states with different data types to share logic area while minimizing unnecessary use of power in a configurable processor. Embodiments include allowing configurable processor designers to describe alias register files and states. Using alias register files and states, designers can implement vector and scalar operations on different register files, but the scalar register file can be implemented on the vector register file. In addition, the upper lanes of the vector register file can be clock gated when the scalar operation performs computations. With this gating, the clocks for the entire upper lanes (including the register file, state, semantic, mux, decoder) can be disabled, which provides power savings.

Abstract: Embodiments of the invention provide an apparatus and method for a coherent, efficient, and configurable cyclic check redundancy retry implementation for synchronous dynamic random access memory. The process includes storing write commands as groups of bursts in a storage location where those commands are stored at least until a time frame has passed for receiving a corresponding cyclic redundancy check failure message. In some embodiments, the process includes retrying corresponding groups of bursts after receiving a failure message where retried groups of bursts are given priority over other memory access commands. In some embodiments, when a read command is received corresponding to a write command that is not beyond the relevant time frame the read command will also be held back from execution until the corresponding time frame has passed without notification of cyclic redundancy check value failure.

Abstract: A system and method are provided for controlling access to a memory device having adaptively split addressing of error-protected data words according to an inline memory storage configuration. An address translation section executes to convert a data address associated with a received command to inline data and inline error checking addresses corresponding thereto. Each data word's data and error checking bits are stored according to respective inline data inline error checking addresses. A segment of error checking bits is thereby offset in address from at least one segment of the same data word's data bits in a common chip of the memory device. A command translation section executes to convert between a received command to data access and error checking access commands for actuating respective access operations on the memory device. An error checking storage section intermediately stores error checking bits responsive to execution of the error checking access command.

Abstract: A method for converting real number modeling to cycle-driven simulation interface file is provided. The method includes verifying an input in a file that includes a real number modeling code, cleaning the real number modeling code in the file, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. Converting the method includes building a definitions file storing a width of at least one real number in the circuit design, and selecting a real number modeling file from the circuit design. For the real number modeling file, the method includes parsing the real number modeling file, building a header file associated with the real number modeling file, and building a compilation file associated with the cycle-driven simulation interface file. A system and a non-transitory, computer readable medium to perform the above method are also provided.

Abstract: A method for assertion debugging may include identifying in signals relating to an execution run of a code a segment of time for which an assertion has failed. The method may also include searching in the signals relating to that execution run, or in signals relating to another execution run of that code, to find one or a plurality of segments of time in which the signals are similar to the signals in the identified segment, for which the assertion was successful.

Abstract: A view definition analyzer maps a plurality of timing views for a circuit design into compatibility groups having shared operating conditions of their respective process corners. An ETM generator then extracts an extracted timing model from a block of the circuit design for each compatibility group, containing timing arcs representing each combination of interface path in the circuit block and timing view in the compatibility group, where at least one timing arc in the ETM is a merged version of multiple timing arcs for an interface path across multiple timing views in the compatibility group. Timing arcs are merged when each timing characteristic in a first timing arc matches, within a tolerance threshold, a corresponding timing characteristic in a second timing arc. The ETM may then be used to model any timing view in the compatibility group. The ETM generator thus produces a minimal set of extracted timing models.

Abstract: The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain additional aspects, embodiments include a power grid optimizer for optimizing portions of a power grid based on analytics such as QOR analytics, and incrementally updating the power grid to include these optimized portions.

Abstract: Disclosed herein are embodiments of systems, methods, and products using a center access direction for pin figures during an abutment of instances in an integrated circuit (IC) design. Using a center access direction allows an electronic design automation (EDA) tool to overlap the centers of the pin figures to be merged. Once the centers of the pin figures are overlapped, the EDA tool runs one or more merging and optimization algorithms to abut the circuit devices containing the pin figures. The EDA tool therefore is computationally efficient and yet provides more functionality: unlike the conventional system, the EDA tool does not have to align the pin figures and calculate an offset to overlap the pin figures post alignment. Furthermore, the EDA tool can overlap the pin figures from any angle and is not confined to rectilinear access direction of the conventional systems.

Abstract: Various embodiments implement an electronic design with power gate analyses using time varying resistors. Design data of an electronic design or a portion thereof may be identified at an electronic design implementation module. First stage electrical characteristics may be generated at least by performing a first stage electrical analysis on a reduced representation of the electronic design or the portion thereof. Second stage electrical characteristics may further be generated at least by performing a second stage electrical analysis on a parasitic injected representation of the electronic design or the portion thereof with a time-varying model for the power gate. The electronic design or the portion thereof may then be further implemented based in part or in whole upon the one or more electrical analyses or simulations.

Abstract: Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a load-balancing process. In another embodiment, the methods use a local cleanup process to rewire the nodes between neighboring clock buffers to further reduce the amount of clock-gaters.

Abstract: The present disclosure relates to a system and method for constraint validation in an electronic design. The method may include receiving an electronic design at an electronic design automation application and analyzing at least a portion of the electronic design at a constraint validation tool configured to analyze one or more physical constraints in a design layout associated with the electronic design. The method may further include applying one or more programmable electrical rule check (“PERC”) rules and one or more constraints to the electronic design, wherein the one or more PERC rules are configured to perform one or more electrical rule checks.

Abstract: Disclosed are methods, systems, and articles of manufacture for dynamically abstracting virtual hierarchies for an electronic design. These techniques identify at least a portion of a layout of an electronic design and a virtual hierarchy in the layout portion according to a value for a display stop level. A plurality of figure groups at one or more virtual hierarchies in the layout portion may also be identified in the layout portion. These techniques select a plurality of layout circuit component designs according to the virtual hierarchy. The layout portion may then be abstracted into an abstracted layout portion at least by displaying the plurality of layout circuit component designs and suppressing one or more remaining layout circuit component designs.

Abstract: Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.

Abstract: Various embodiments implement an electronic design with automatically generated power intent. One or more inputs to a physical electronic design implementation module may be identified for power intent generation for an electronic design. The power intent for the electronic design may be generated by using at least one or more power related characteristics that are determined from at least the one or more inputs for the power intent generation. With the generated power intent, the electronic design may be implemented at least by guiding the implementation of the electronic design with at least the generated power intent while reducing usage of one or more computing resources.

Abstract: An improved approach is provided to generate and display waveform data, where data reduction is intelligently applied to create filtered waveform data. By reducing the quantity of the waveform data in an intelligent manner, this permits the waveform display tool to process the waveforms quickly enough for interactive usage, while still retaining sufficient data fidelity for accurate data analysis and waveform visualization.

Abstract: A method to initiate Command Address (CA) training on High Memory Bandwidth is provided to optimize CA bus setup and hold times relative to the memory clock. HBM protocol does not define any way to support CA training, but defines a very high working frequency. The high frequency makes it very difficult to ensure the timing on CA Bus-Row/Column command bus and CKE. As such, executing CA training before any normal operation is necessary to ensure the best setup/hold timings. The CA training takes advantage of protocol based instructions to initialize and implement CA training.

Abstract: Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.