Abstract: Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback equalization and continuous time linear equalization.

Abstract: A method for identifying a potential cause of a failure in simulation runs on a design under test (DUT) using machine learning is disclosed.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and performing formal verification upon at least a portion of the electronic design. Embodiments may further include identifying one or more violations associated with the formal verification and ranking the one or more violations, based upon, at least in part, one or more user-selectable variables. Embodiments may also include displaying, at a graphical user interface, the one or more violations in a ranked order.

Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from receiver arrangements that are not in autozero mode using multiplexer circuitry. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

Abstract: The present disclosure relates to an apparatus and method for correcting a duty cycle of at least one signal. The apparatus may comprise at least one set of inverters configured to receive the at least one signal and correct the duty cycle of the at least one signal at a correction location of a plurality of correction locations based upon, at least in part, a transmission rate mode of a plurality of transmission rate modes.

Abstract: A receiver device includes circuitry and memory. The circuitry converts an input signal into a data signal that includes data symbols transmitted in successive unit intervals (UIs), determines a first threshold associated with a first symbol type, adjusts a gain of the receiver device such that an average amplitude of data signal samples, when receiving data symbols having the first symbol type, corresponds to the first threshold, determines a second threshold that corresponds to an average amplitude of the data signal samples when data symbols of a current UI have the first symbol type and data symbols of a first UI, at a first determined time distance from the current UI, have a second symbol type, and computes, as a first cursor value associated with the first UI, a first difference between the first threshold and the second threshold, multiplied by a first constant.

Abstract: A method for functional safety verification for use in a verification of a design under test (DUT), includes obtaining a set of verification tests previously executed on the DUT and related execution data; injecting a fault into each of the tests of the set of verification tests; analyzing a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree; and for each of the clusters of faults, based on the execution data, performing test ordering of tests from the set of verification tests according to likelihood of classifying the faults under the child node in which that cluster is located.

Abstract: Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be executed in any order upon request or are hard-coded in a specific order.

Abstract: The present embodiments relate to critical path aware voltage drop analysis. A method can include identifying a number of cell instances with largest individual power consumption values. The method can include identifying, by performing static timing analysis, a first number of circuit timing paths of an integrated circuit design with largest timing violations. The method can include identifying, by performing the static timing analysis, a second number of circuit timing paths of the integrated circuit design. Each of the second number of circuit timing paths has a timing violation and is formed by one or more of the identified number of cell instances. The method can include generating logic state toggle vectors by propagating logic states through the first and second numbers of circuit timing paths. The method can include performing voltage drop analysis on the integrated circuit design using the generated logic state toggle vectors.

Abstract: An exemplary emulation computer may allocate a portion of its emulation memory for capturing probe data during a runtime of emulating a device under test (DUT). The emulation computer may instantiate a plurality of streaming probes from dynamic netlists provided by a user. The streaming probes may capture non-transitory internal signals within the DUT and transmit the captured non-transitory internal signals to the allocated portion of the emulation memory, which in turn may store the received signals as waveform data records. During the runtime of emulating the DUT, the emulation computer may receive an upload request for the waveform data records from a workstation computer. In response to the request, the emulation computer may transmit the waveform data records to the workstation computer. The emulation computer does not have to pause or stop the runtime of emulating the DUT while transmitting the data records to the workstation computer.

Abstract: The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain aspects, the language further allows designers to specify additions/subtractions to the core grid over macros and secondary power instance groups. According to still further aspects, embodiments allow for incremental repairs of only specific portions of the power grid.

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.

Abstract: A method including creating a plurality of component groups in a circuit layout coupling multiple components in each component group of the plurality of component groups with a power rail, a ground rail, or a bulk, is provided. The method includes creating internal clusters based on a group cost and including the group cost in an overall cost function, forming a gap between two component groups of the plurality of component groups, and filling the gap with a first gap cell adjacent to a first power rail and to a first ground rail, and a second gap cell adjacent to the first gap cell. A system and a non-transitory, machine readable medium storing instructions to perform the above method are also provided.

Abstract: An emulation system comprises an outband traffic generating device comprising at least one field programmable gate array coupled to a host system. The outband traffic generating device is configured to transfer one or more bits via an outband channel to a register of an inband traffic generating device. The inband traffic generating device comprises at least one field programmable gate array coupled to a target system. The inband traffic generating device is configured to transfer the one or more bits via an inband channel to the outband traffic generating device.

Abstract: The present disclosure relates to an apparatus including level shifter circuitry configured to convert a voltage between one or more multi-voltage domains. The apparatus may include an integrated circuit having a cross-coupled latch including a first weak transistor cross-coupled with a second weak transistor. The integrated circuit may further include a first strong transistor in parallel with the first weak transistor and a second strong transistor in parallel with the second weak transistor. The integrated circuit may further include an inverter configured to toggle at least one of the first weak transistor and the second weak transistor.

Abstract: The present disclosure relates to a computer-implemented method for analyzing one or more hyper-parameters for a multi-layer computational structure. The method may include accessing, using at least one processor, input data for recognition. The input data may include at least one of an image, a pattern, a speech input, a natural language input, a video input, and a complex data set. The method may further include processing the input data using one or more layers of the multi-layer computational structure and performing matrix factorization of the one or more layers. The method may also include analyzing one or more hyper-parameters for the one or more layers based upon, at least in part, the matrix factorization of the one or more layers.

Abstract: Disclosed herein is an apparatus and method for emulating hardware. The apparatus includes a data array configured to store input data for an emulation cycle and a carry chain coupled to the data array receives one or more inputs from the data array. The carry chain is configured to generate output data in response to performing an arithmetic operation by a set of configurable logic gates using the one or more inputs in a pre-determined number of clock cycles. One or more processors are coupled to the carry chain and the data array, and are configured to emulate a logic gate function using at least the input data from the data array or the output data from the carry chain.

Abstract: A device including an address extraction for a data burst associated with a host processor and to map the data burst to a memory according to a rotation is provided. The device includes a splitter to separate a first command that associates the data burst with a first round in the rotation, and a selection logic to select, from the first round in the rotation, a first bank group at the address in the memory to execute the first command, and execution logic to receive the data burst and the address in the memory to activate the first bank group at the address in the memory, and to schedule an execution of the first command based on an availability of a second bank group from the first round in the rotation. A system and a non-transitory computer readable medium storing instructions to use the device are also provided.

Abstract: A system and methods to verify a correctness of data formatted according to an IEEE P1687 (IJTAG) standard, in connection with migration of test patterns from an instrument level to a top level of an integrated circuit design. Data describing an integrated circuit at the instrument level and at the top level is read from Instrument Connectivity Language (ICL) files, Procedural Description Language (PDL) files, and hardware description language (HDL) files. The methods include at least one of verifying structural descriptions of the integrated circuit in the ICL files and verifying an ability to use chip level inputs to access instruments in the integrated circuit. The verification procedure is performed prior to a simulation in which a migrated test pattern is applied to the integrated circuit.

Abstract: A method for automated selection of a subset of a plurality of validation tests for testing a device under test (DUT), may include obtaining the plurality of validation tests; using a processor, obtaining from a user, via an input device, one or a plurality of conditions relating to one or a plurality of execution parameters; and using a processor, analyzing each of the validation tests to identify a subset of the validation tests that includes verification tests conforming to said one or a plurality of conditions.