Abstract: The present embodiments relate to generation of an interface model for performing a power analysis on a hierarchical integrated circuit design. According to some aspects, embodiments relate to a method of power analysis. The method can include partitioning an integrated circuit design into at least a first partition and a second partition sharing an interface with the first partition. The method can include generating a connectivity database of a signal net traversing from the first partition to the second partition across the first interface. The method can include determining a slew rate and a signal arrival time at the input pin of the destination cell, a capacitance load of the signal net, and one or more signal transitions and signal states on the signal net. The method can include calculating the power consumption of the circuit elements in the first partition using the connectivity database, and the determined information.

Abstract: Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first wire based at least in part on the misalignment value. In some embodiments, all wires in various routings of a circuit design are checked for possible misalignment in order to improve slew performance via reduction of unnecessary vias.

Abstract: Systems, methods, and products having pipelined inputs to and outputs from an emulator are disclosed. Using a pipeline may allow the round trip cable delay (RTCD) to be spread across two or more clock cycles. In an embodiment, an emulation system may store input data received from a target device during a first clock cycle at a target timing domain interfacing component (TTD), and transmit the stored input data during a second clock cycle after the first clock cycle. In another embodiment, the emulation system may delay transmitting the input data received at the TTD during the first clock cycle such that that the input data reaches the emulator at a predetermined time during the second clock cycle. As the RTCD is spread across multiple clock cycles, the emulation system may implement faster clocks.

Abstract: Disclosed herein are systems and methods of an emulation system. A hardware emulator of an emulation system includes a method of hardware emulation on a computer. The method may include reading in, by the computer, a hardware description language file and a low power intent file and compiling the hardware description language file and the low power intent file into an emulation image. Embodiments may include loading, the emulation image into an emulator, running, the emulation image under a test environment including using a coverage counter specific to low power coverage, created based on the hardware description language file and the low power intent file, using the coverage counters to inform the test environment, generating, by the computer, a report file including a set of low power coverage metrics based on a low power coverage data item, and presenting the report file to a user via a user interface.

Abstract: An exemplary fuse control arrangement can be provided, which can include, for example, a fuse control unit(s), which includes a test access method interface(s) and a programmable memory(ies), wherein the fuse control unit(s) is configured to provide fuse information to repair a memory(ies). The fuse control unit(s) can be coupled to the memory(ies) and the memory(ies) can be coupled to a register repair unit(s). The fuse control unit(s) can provide the register repair unit(s) with the fuse information to repair the memory(ies).

Abstract: A circuit editor generates a graphic rendering of an electronic circuit design for partial display in a visual canvas on a display unit. The circuit editor detects aberrant arrangements of circuit elements which violate predetermined circuit layout criteria, such as minimum spacing between the edges or corners of circuit elements, and forms a correction scheme to rearrange the circuit elements such that consistency with the circuit layout criteria is restored. When the aberrant arrangements are not themselves displayed in the visual canvas, the circuit editor generates visual indications of the layout violation and of the correction scheme, the latter being used to guide user correction of the violation.

Abstract: Disclosed are techniques for implementing group legal placement on rows and grids for an electronic design. These techniques identify a group comprising a plurality of instances. A proxy is identified from the plurality of instances. The group is placed in a row region based in part or in whole upon a plurality of permissible characteristics for the proxy without considering permissible characteristics of one or more remaining instances in the group. A group legality may be performed to determine whether the group is placed in the row region in a group legal manner.

Abstract: A method for generating a validation test, may include obtaining, using a processor, a validated scenario for generating a test for a verification model, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph. The method may also include analyzing, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with a faulty scheduler of a verification model to be tested. The method may further include, upon identifying the identified action, amending, using the processor, the verified scenario by removing the identified action from the graph.

Abstract: The present disclosure relates to non-linear systems associated with an electronic circuit design. Embodiments may include identifying the non-linear system associated with the electronic circuit design and determining a degree of severity of non-linearity of the non-linear system associated with the electronic circuit design. If the degree of severity is less than a predefined threshold, embodiments may further include receiving a random input pattern and deriving a single impulse response characterization, wherein the random input pattern is based upon, at least in part, an electronic circuit simulation associated with the electronic circuit design.

Abstract: Disclosed herein are embodiments for generating hierarchical rotating pcells (parametrized cells) design from a user provided static hierarchical design. An EDA (Electronic Design Automation) tool may receive a hierarchical static design and allow the user to instantiate a top level hierarchical rotating pcell using one or more parameters including an angle parameter to indicate a rotation angle. Based on the one or more parameters, the EDA tool may recursively identify, in the user's static hierarchical design, lower level static cells and replace them with the hierarchical rotating pcells based on the angle parameter in the already instantiated upper level hierarchical rotating pcells. The EDA tool may instantiate and re-instantiate hierarchical rotating pcells until leaf-level cells have been reached to dynamically generate an IC (integrated circuit) design with hierarchical rotating pcells from the user's static hierarchical design such that rotation can be accomplished without flattening the IC design.

Abstract: Various embodiments described herein provide a multiple injection lock ring-based PI that can inject a plurality of clock signals, of different phases, at injection points disposed along the ring chain of the PI and lock phase to those received clock signals (injected clock signals). For instance, an embodiment described herein may provide a multiple injection lock ring-based PI that permits double injection, triple injection, or the like, of clock signals external into the PI.

Abstract: A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a prototyping platform to stop when the assertion control signal is enabled in the assertion checker and a logic condition for the assertion control signal is satisfied in the prototyping platform. A system and a computer readable medium including instructions to perform the above method are also provided.

Abstract: Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree, and specific portions of the design are routed individually from other portions of the design.

Abstract: In an electronic circuit design system, a physical layout of at least part of an electronic circuit design is visually rendered. Magnitude of current loading are determined at one or more of the circuit nodes, or one or more clusters of nodes grouped according to predetermined clustering criteria, for a selected net or nets. The range of magnitudes is mapped to at least one gradation range for visual indicia of preselected type, such as a predetermined color spectrum; preferably, alternative gradation ranges respectively for current sources and current sinks are provided. The visual indicia of the current loading magnitudes are then adaptively displayed to overlay the corresponding circuit nodes or clusters in the rendered physical layout, providing a reference for a designer to proportionately size segments of the selected net or nets, as well as spacing required for the segments.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, at least one electronic design file and a set of inputs from a user, wherein the at least one electronic design file and set of inputs are associated with an electronic design. Embodiments may further include performing formal verification on at least a portion of the electronic design and determining, using a model checker, one or more conflicts associated with a variable during the formal verification. Embodiments may also include translating the one or more conflicts into one or more corresponding signal names and displaying, at a graphical user interface, the corresponding signal names.

Abstract: A method for retrieving a virtual address from a physical address accesses in a memory of a computing system, to which that virtual address was previously mapped to, may include: using a monitor to intercept transmissions to and from a memory of a computing system; using a processor: identifying in the intercepted transmissions page table address calls relating to mapping of a virtual address to a physical address; and retrieving the virtual address from the identified page table address calls.

Abstract: The present embodiments relate to implementing an integrated circuit design where a layout of circuit cells on a semiconductor chip is based on positions of the circuit cells on a schematic. According to some aspects, embodiments relate to a method for identifying a plurality of sub-regions on a semiconductor chip layout where each sub-region has a placement constraint. The method further includes assigning circuit cells to sub-regions based on the constraints. The method also includes clustering the circuit cells into clusters based on their positions on the schematic. Circuit cells from each cluster are placed in one or more of the sub-regions based on the proximity of the centers of the clusters to the centers of the sub-regions.

Abstract: Disclosed is an improved approach to implement clock alignments between a test subject and its corresponding controller device. Phase locking is performed for the clocks between the test subject and controller device via a training sequence to obtain the appropriate alignment(s). Alignment logic is included on both the testchip and the controller device to implement alignment.

Abstract: The present disclosure relates to a system for use in electronic circuit design. The system may include a computing device configured to receive, using at least one processor, an electronic design. The at least one processor may be further configured to generate a common path pessimism removal (“cppr”) database configured to store one or more cppr tags obtained from an initial timing analysis of at least a portion of the electronic design. The at least one processor may be further configured to apply the one or more cppr tags during a block-level timing analysis.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include receiving, using at least one processor, the electronic circuit design and displaying, via a graphical user interface, a first device associated with the electronic circuit design. Embodiments may further include displaying, via the graphical user interface, a second device associated with the electronic circuit design. Embodiments may also include displaying, via the graphical user interface, inter-device connectivity between the first device and the second device and displaying intra-device connectivity between at least one of the first device and the second device, wherein the inter-device connectivity and the intra-device connectivity are visibly distinct.