Abstract: Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

Abstract: The present disclosure relates to systems and methods for performing out of order name resolution in an electronic design language. Embodiments may include receiving, one or more design units associated with an electronic design and registering the one or more design units in a registry database. Embodiments may further include performing local name resolution for each element reference within at least one of the one or more design units. In response to registering, embodiments include identifying at least one element reference upon which local name resolution was not performed and obtaining an appropriate element reference from the registry database. Embodiments may further include reviewing at least one secondary design unit for one or more local declarations and performing local name resolution for one or more remaining element references using a design hierarchy.

Abstract: Aspects of the present disclosure include a frequency-to-current (F2I) circuit and systems, methods, devices, and other circuits related thereto. The F2I circuit is implemented with a delta-modulator-based control loop to settle and maintain an operating point on a bias node. The control loop provides an integral of an output of a comparator, and the comparator compares it to a self-built voltage reference. Upon powering on the circuit, an integrator in the control loop starts to integrate the charge on both a bias voltage and an internal voltage to provide a settling process for the internal voltage to approximate the reference voltage and for the bias voltage to approximate a predetermined operating point of the bias node. After the circuit has settled, the comparator's output charge toggles and the internal voltage and bias voltage become sawtooth-like waveforms at the reference voltage and operating points, respectively.

Abstract: Embodiments of the invention provide an approach to implement a single architecture to support high bandwidth memory of pseudo channel mode or legacy channel mode by using a single command channel and single data channel. An address mapping method forces each port transaction to alternatively split to two pseudo channels. Compared to the conventional pseudo channel architecture, the single architecture and pseudo channel rotation eliminates the need for duplicated command traffic logic, and a time division command arbitrator, which greatly reduces both control logic and power consumption of the circuits. Furthermore, pseudo channel rotation improves the utilization of memory bandwidth because the address mapping improves synchronization of the two pseudo channel traffics.

Abstract: Disclosed is an improved approach to implement selective transformations of circuit components for performing verification. The approach looks at the observability of components to downstream properties to determine whether transformations are needed. The verification system leverages the knowledge about the behavior of the domains/components to identify only a subset of components that really need to undergo transformation.

Abstract: The present disclosure relates to a system and method for use in a digital signal processing environment. Embodiments may include a programmable processor configured to execute an instruction set that includes multiply instructions and/or multiply-accumulate instructions that generate a result in carry-save format or redundant binary format. The instruction set may be executed at a single instruction, multiple data (SIMD) level.

Abstract: Embodiments relate to circuits, electronic design assistance (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on different supply voltages. In one embodiment, a programmable level translator device is implemented using an NMOS transistor pair and a PMOS cross quad. The switching characteristics are modified with the use of a charge pump connected to the gate terminals of two of the PMOS transistors within the PMOS cross quad. Transmission gates are also employed to engage and disengage the charge pump based on a control switch. In various embodiments, the level translator device works with a number of memory devices operating over a wide range of power supply voltages.

Abstract: A method for synchronizing transactions between components of a system on chip includes monitoring a partial sequence of transactions that use AXI communication protocol for a stream of address calls and a streams of transfer batches. For each of the address calls and transfer batches identified by the same unique identifier, extracting an anticipated an anticipated number of transfers per batch from each of the address calls of the stream of address calls, and recursively, comparing the anticipated numbers of transfers extracted from the address calls of the stream of address calls with the number of transfers in the transfer batches of the stream of batches. Pairing a predetermined number of consecutive address calls of the stream of address calls with consecutive batches of the stream of batches based on the comparison.

Abstract: Recording and playback of trace log data and video log data for programs is described. In one aspect, a method for viewing log data recorded during execution of a program includes causing a display of recorded images depicting prior visual user interaction with the program during a particular time period. The method also includes causing a display of messages tracing and describing prior execution of the program during the particular time period. The display of the messages and the display of the recorded images are synchronized.

Abstract: Disclosed are techniques for multi-mode, multi-corner physical optimization of electronic designs. These techniques identify an electronic design and a global set of views. Timing information is characterized with the global set of views for the electronic design. A set of active views is generated at least by pruning one or more views from the global set of views for a first node in the electronic design while maintaining the one or more views for a second node in the set of active views. The electronic design is then associated with the set of active views that is stored in a data structure in a non-transitory computer accessible storage medium.

Abstract: Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

Abstract: A system and method are provided for reducing processing time in characterizing a programmably implemented cell. The cell is decomposed into a plurality of channel connected component portions (CCC's), each including a local output node and at least one switching device establishing a conduction channel within a channel path extending from the local output node to a power plane of the cell. A component characteristic function is generated for each CCC, which logically sums a locus of vectors for nodes electrically connected to the local output node. Each CCC's component characteristic function is expanded to form a local characteristic function relative to one or more other upstream CCC. Each local characteristic function is thereby formed exclusive of any upstream local output node electrically disconnected from its local output node. At least one feasible vector is selectively generated from the local characteristic functions according to requirements predefined for a parametric measurement.

Abstract: The present disclosure relates to a computer-implemented method for visualizing internal instance structure and connections in a design system component. Embodiments may include receiving, using at least one processor, an IP-XACT description of one or design elements and analyzing, using the at least one processor, the IP-XACT description of the one or design elements. Embodiments may further include displaying a graphical user interface, based upon, at least in part, the IP-XACT description of one or design elements, wherein the graphical user interface is configured to display a self-organizing graphical layout including a parent component, at least one node, and at least one edge.

Abstract: The present disclosure relates to defining and processing hardware description language (HDL) groups. Embodiments may include mapping, using a processor, a set of tool-specific objects into a group graph with one or more groups. Embodiments may also include generating a search order associated with each group. The search order associated with each group may be based upon the hierarchical design configuration of the group graph. Embodiments may further include identifying undefined references from within a first group within the group graph and binding defined references from within the first group to electronic circuit design components. Embodiments may include identifying the undefined references from within a second group within the group graph. The second group may be selected based upon the undefined references and the search order associated with the first group.

Abstract: A benchmark test system captures and records root, or input, behavior from a user input device as one or more time-displaced samples of input. The system also separately captures and records the canvas, or visual, behavior of a user interface in response to the captured input as a series of time-displaced image frames. The image frames are analyzed for visual prompts occurring responsive to the input, and parameters of the image frames are determined. A parametric difference between corresponding ones of the root events and canvas responses is thereby computed, in order to determine a degree of visual responsiveness for the user interface software respective to the root input.

Abstract: A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.

Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation is provided. Embodiments may include providing, using one or more processors, an electronic design configured to generate one or more address sequences. Embodiments may also include applying an address noise monitor to the electronic design, wherein the address noise monitor is configured to determine address noise data, wherein the address noise data includes a measure of one or more discontinuities in the one or more address sequences. Embodiments may further include simulating the electronic design to generate one or more performance results, the one or more performance results including address noise data. Embodiments may also include generating an address noise profile, based upon, at least in part, the one or more performance results including address noise data.

Abstract: An improved approach is provided to provide fast access to waveform visualizations for electronic designs. Data reduction is performed on the waveform data, where the quantity of the waveform data is reduced in an intelligent manner, such that the reduced waveform data still retains sufficient data fidelity for accurate data analysis and waveform visualization. The reduced data can then be displayed in an accelerated manner. From the display of the reduced data, this allows the user to select only the specific one or more waveforms for which the user seeks viewing of the full waveform data.

Abstract: A method for performing a regression session when testing a device under test (DUT), may include a. obtaining a coverage model of the DUT, and a verification session input file (VSIF) relating to a plurality of tests to be run on the DUT, the VSIF including an initial number of runs associated with each of the tests of the plurality of tests; b. performing a first iteration of the regression session in which each of the tests of the plurality of tests is run the initial number of runs associated with that test; c. calculating for that iteration an effectiveness grade of each run of the tests of the plurality of tests, and assigning a weight to each of the runs of the tests of the plurality of tests corresponding to the calculated effectiveness grade of that test run; an d.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing deadlock detection with formal verification techniques in an electronic design. These techniques identify one or more inputs that include at least an initial state of an electronic design and identify at least one deadlock candidate by sweeping at least a portion of a state space of the electronic design with formal verification techniques. These techniques then determine whether the at least one deadlock candidate is a real deadlock by using a second formal search with the formal verification techniques.