Abstract: Various embodiments provide for generation of a clock tree for a circuit design using a mix of a set of buffers and a set of inverters. Some embodiments balance use of buffers and inverters such that the generated clock tree leverages buffers to lower driver count and clock tree, and leverages inverters for lower power usage and duty cycles.

Abstract: The present embodiments relate generally to integrated circuit design, and more particularly to techniques that automatically and dynamically create or adjust a highlight set in a graphical user interface for allowing designers to edit layouts in a hierarchical design in a more productive manner. According to certain aspects, in dense designs and/or designs having complete or partial overlapping shapes, embodiments allow for highlighting more than one hierarchy level with tuned parameters that improve the user experience and enhance user work productivity. According to other aspects, embodiments allow for highlighting shapes using colors and/or widths that allow both highlight and shape to be clearly visible and distinguishable.

Abstract: Disclosed are methods, systems, and articles of manufacture for manipulating a hierarchical structure of the electronic design. These techniques identify a set of layout components instantiated from a layout of an electronic design. This set of layout components may constitute, for example, a FigGroup. One or more schematic instances and corresponding schematic connectivity information may be identified from a schematic design of the electronic design, and the one or more schematic instances correspond to the set of layout components. A layout cell or a figure group may be generated for the set of layout components based in part or in whole upon the schematic connectivity information. The original layout may then be transformed into a transformed layout at least by replacing the set of layout components with the generated layout cell or figure group.

Abstract: Systems and methods disclosed herein provide for adaptively applying pattern filters so that the edges are discarded only when the DFE feedback has adapted to levels that can corrupt the timing recovery. Embodiments of the systems and methods provide for a phase detector that selectively suppresses timing information based on the logic level states of the Qp and Qm data samples associated with the received signal.

Abstract: The present embodiments relate to methods and apparatuses for detecting a codeword boundary and/or performing codeword error correction for a bitstream comprising scrambled Reed Solomon codewords. In accordance with some aspects, detecting a codeword boundary involves the use of the parity and symbols from a previous window to help in detecting a codeword boundary when the next input bit is received. In accordance with other aspects, parity symbols are more efficiently updated for each successive candidate input bit. In accordance with still further aspects, error correction during codeword boundary detection can be either partially performed or completely bypassed.

Abstract: Aspects of the present disclosure include systems, methods, devices, and circuits for fast settling of a bias node. Consistent with some embodiments, a bias circuit may include a successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop configured to perform a fast settling process for a heavily loaded bias node. The SAR-ADC based loop performs a SAR-ADC process that includes measuring a reference signal to determine a number of cells in a capacitor array that are involved in a charge sharing process while simultaneously completing the settling process for the bias node.

Abstract: An improved method, system, and computer program product to perform post-layout simulation of an electronic design is provided. According to one approach, a circuit design is divided into multiple partitions for simulation. Simulation is then performed using the established partitions and results are obtained for the different partitions. When any layout editing occurs, identification can be made of any partitions that have been affected by the editing. The affected partitions are re-processed for simulation. The unaffected partitions do not necessarily need to be reprocessed.

Abstract: Aspects of the present invention describe a system and method for providing a single integrated simulation interface running in a single host operating system (OS) thread to observe and control multiple, disparate software and hardware components. Control mechanisms of the present invention provide access to each of the modeled components, including the hardware models, the embedded software components modeled on the bare-hardware elements, and the software applications, processes and threads which are themselves running on embedded software.

Abstract: A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.

Abstract: Aspects of the present disclosure include systems, methods, devices, and circuits for correcting integral non-linearity using a hybrid phase interpolator. Consistent with some embodiments, a circuit comprises a first and second phase interpolator mixer connected to an injection-locked ring. The first phase interpolator mixer provides a first injection signal to the injection-locked ring based on a clock signal, and the second phase interpolator mixer provides a second injection signal to the injection-locked ring. The first and second injection signals have inverse step size profiles. The injection-locked ring generates a first and second output clock phase based on the first and second injection signals. In generating the first and second output clock phases, the injection-locked ring averages the step size profiles of the first and second injection signals.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing virtual prototyping for electronic designs. These techniques identify a plurality of leaf cells into a hierarchical physical design of an electronic design, generate the hierarchical physical design at least by performing hierarchical placement for the plurality of leaf cells based in part or in whole upon one or more factors, and revise the placed hierarchical physical design at least by performing hierarchical routing for the plurality of leaf cells on the hierarchical physical design. One aspect may further detach a virtual cell in the hierarchical physical design at least by grouping a first set of leaf cells and representing the first set of leaf cells with a first placeholder.

Abstract: Systems disclosed herein provide for efficient top-level compactors for systems on a chip (SoCs) with multiple identical cores. Embodiments of the systems provide for compactors with a time-skewed assignment configuration, compactors with a space-skewed assignment configuration, compactors with time/space-skewed assignment configuration, and compactors that can selectively switch between the time/space-skewed assignment configuration and a symmetric assignment configuration.

Abstract: Various embodiments provide for a level shifter with sub-threshold voltage functionality, which permits the level shifter to operate even when a voltage supply to the level shifter falls below a normal operational voltage range of one or more devices (e.g., transistors) within the level shifter. A level shift of an embodiment may operate when a voltage supply falls below a normal operational range in order to save power, which can be useful with respect to battery-operated devices, such an Internet of Things (IoT) sensor.

Abstract: The present disclosure relates to a method for reusing a debugging workspace in an electronic design environment. Embodiments may include performing, using a processor, a verification of an electronic design and identifying at least one triggered property associated with the electronic design. Embodiments may further include identifying at least one fan-in signal associated with the at least one triggered property of the electronic design. Embodiments may also include determining a start point debug location based upon, at least in part, the at least one fan-in signal, wherein the start point debug location includes at least one of signal information, cycle information, and event time information. Embodiments may further include generating a debug workspace, wherein generating includes adding at least one additional debug location and storing a cycle of the additional debug location as a relative cycle that is relative to another debug location associated with the debug workspace.

Abstract: An integrated circuit test method provides an interactive shell environment having analysis modules organized as a directory such that for a given session a user can access any of the analysis modules. This invention describes a virtual directory structure for navigating through the entire test data starting from design, test configuration, ATPG patterns, failure information and callout information. This structure also allows the creation of a scripting environment for the user to select a specific configuration and process the information. User can achieve all of this in a single session as opposed to working on every test configuration in an independent session.

Abstract: A control-circuit of an emulation system may include one or more serial link inputs communicatively coupled to a serial bus, a serial link input receiving an input control bit from the serial bus. A configurable logic circuit may be configured to receive multiple control bits from the one or more serial link inputs, execute one or more operations on the plurality of input control bits according to programmable logic, and transmit an output control bit to a serial output link.

Abstract: The present embodiments relate generally to techniques for creating and/or modifying multi-layer buses in an IC design. According to some more particular aspects, embodiments relate to techniques for allowing an IC designer to efficiently transition a multi-layer bus section made of N wires and M layers to another multi-layer bus section made of N wires and any other M? layers. In some embodiments, the user describes, programmatically, one or several custom transitions called a custom transition procedure and saved in a human-readable text file that can also be read by a layout editor tool. By a command associated with the custom transition procedure that is exposed to the user in the layout editor tool, a multi-layer bus is automatically transitioned from a set of layers to another.

Abstract: Methods for debugging a failure in a logic circuit design simulation by tracing a X-value are provided. In one aspect, a method includes detecting during a X-propagation logic circuit design simulation a failure at a register transfer level of a logic circuit comprising one or more logic blocks and tracing a X-value in a data path of the one or more logic blocks until the X-value is observed in a control path of the one or more logic blocks. The method also includes identifying a logic block comprising a control signal of the control path in which the X-value is observed, and identifying the logic block in which the X-value is observed as a root cause of the failure. Systems and machine-readable media are also provided.

Abstract: A system, methods, and a computer program product for estimating a yield and creating corners of a circuit design with the aid of a failure boundary classification. The system, methods and computer program product provide for determining, based on how many sampling factors have failures, whether data samples are sufficient as input to scaled-sigma sampling. If the data samples are insufficient, the failure boundary classification is usable to determine whether the yield is high enough to meet a yield target. A design corner can be located by applying a binary search to results of scaled-sigma sampling. The failure boundary classification can aid in setting up the search.

Abstract: Various embodiments provide for analyzing impedance states of a set of nodes in a circuit design and providing a set of reasons for those impedance states. The set of reasons can include a reason regarding why a particular node is reported as being in high-impedance (highz) state or in low-impedance (lowz) state, and the reason may be for a specific time point during transient analysis of the circuit design. Some embodiments are implemented within a debugging utility of an electronic design automation (EDA) software system.