Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, at an electronic design associated with one or more computing devices, a differential pair between a driver and a receiver. The method may further include identifying one or more segments associated with the differential pair and automatically solving, using the one or more computing devices, for a dynamic phase associated with the one or more segments.

Abstract: The present embodiments relate to reconfiguration of a schematic. According to some aspects, embodiments relate to a method in which a schematic of a circuit is displayed on a graphical user interface of a computing device. The schematic can include a plurality of circuit objects, and at least one interconnect connecting the plurality of circuit objects to define a circuit connectivity. The method further includes defining a schematic reference point on the schematic. The method also includes determining a distance of each circuit object of the plurality of circuit objects from the schematic reference point. The method also includes increasing the distance of each circuit object of the plurality of circuit objects from the schematic reference point relative to a respective size of each circuit object, wherein increasing the distance includes multiplying the distance by a scaling factor. The at least one interconnect is reconfigured to maintain circuit connectivity.

Abstract: Embodiments of the invention provide a command-oriented method to lower power consumption of PHY during idle time periods. The idle time periods occur because HBM Commands have certain timing windows where there is no data transmission on DFI data signals between the memory controller and the PHY data slice. These windows may be utilized to power down the PHY data slice data path through DFI signal handshaking. In contrast to the conventional low power mode, this method provides an advanced low power mode that can further reduce power consumption in different modes at each suitable idle time based on different command types.

Abstract: Various techniques implement an electronic design with electrical analyzes with compensation circuit components. A power pin of a power net may be identified in an electronic design. The electronic design may be reduced into a reduced electronic design at least by applying one or more circuit reduction techniques to at least a portion of the electronic design. At least one load device of a plurality of load devices in the reduced electronic design may be transformed into a transformed load device. One or more design closure tasks may be performed on the electronic design using at least the reduced electronic design and the transformed load device.

Abstract: Aspects of the present disclosure address improved systems and methods for region-aware clustering in integrated circuit (IC) designs. Consistent with some embodiments, the method may include identifying a clustering region for each clock driver included in an IC design based on locations of sinks and blockages, and timing constraints. The CTS tool finds representative locations for each clock driver within their respective clustering regions. Given the representative location for each clock driver, the CTS tool applies point-based clustering to the clock drivers of the IC design to obtain one or more clusters.

Abstract: The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include storing a lock list at a client computing device, wherein the lock list includes objects associated with an electronic design that have been locked or unlocked. Embodiments may further include receiving a user input corresponding to a lock/unlock request associated with an object of the design, wherein the design is accessible by multiple users in an at least partially concurrent manner. Embodiments may include transmitting the lock/unlock request to a server computing device. Embodiments may further include comparing the user input corresponding to at least one of the lock request or unlock request with the lock list and determining whether to lock or unlock the object based upon, at least in part, the comparison, wherein determining does not include receiving server authorization.

Abstract: The described techniques implement an electronic design with transistor level satisfiability models by identifying a plurality of channel connected components of an electronic design for sensitization. These techniques further determine a set of transistor level satisfiability (SAT) models for the plurality of channel connected components of the electronic design and transform the plurality of channel connected components into a set of conjunctive normal form (CNF) formulae using at least the set of transistor level SAT models. The plurality of channel connected components of the electronic design may be sensitized at least by determining one or more satisfying assignments with the set of CNF formulae. These techniques may also generate transistor level satisfiability (SAT) logic models and transistor level SAT state models for a circuit component based in part or in whole upon design specifications and one or more characteristics of the circuit component.

Abstract: Disclosed are techniques for implementing placement using row templates for an electronic design using row templates. These techniques identify or create a row region in a layout of an electronic design. A row template is applied to the row region to create one or more placement rows in the row region. One or more layout circuit components may then be placed into one or more rows or at one or more locations to create a legal placement layout by guiding placement of the one or more layout circuit components with the row template.

Abstract: Systems, methods, media, and other such embodiments are described for placement of cells in a multi-level routing tree, where placement of a mid-level parent node between a grandparent node and a set of child nodes is not set. One embodiment involves generating a first routing subregion between a first set of child nodes associated with a first grandparent node and a first connecting route from the first routing subregion to the first grandparent node, which together are set as a first routing region comprising the first routing subregion and the first connecting route. Sampling points are selected along the first routing region, and for each sampling point a set of operating values associated with the sampling point is calculated. A position for the parent node is selected based on the operating values for the sampling points.

Abstract: A method for reuse of a refinement file in coverage grading, may include obtaining a refinement file that includes a listing of coverage entities of a first coverage model, for exclusion from a calculation of coverage grading of the first coverage model; obtaining mapping information to map a source path of each of the modules or instances of a module, that include one or more of said coverage entities in the first coverage model to a target path of each of said modules or instances of a module in a second coverage model; and using a processor, based on the refinement file and the mapping information, translating a source path of each of said coverage entities listed in the refinement file to a target path of a coverage entity of the coverage entities in the second coverage model.

Abstract: Various embodiments implement an electronic design with one or more electrical analyses or simulations. Pre-layout and/or post-layout design data of an electronic design or a portion thereof may be identified at a physical design implementation module. A first stage analysis may be performed on the electronic design or the portion thereof at least by computing electrical characteristics with a reduced representation in the electronic design or the portion thereof. Electrical behavior of the electronic design or the portion thereof may be generated at least by performing a second stage analysis on the electronic design or the portion thereof with one or more adjusted electrical characteristics. The electronic design or the portion thereof may then be implemented based in part or in whole upon the one or more electrical analyses or simulations.

Abstract: Disclosed herein are embodiments of systems, methods, and products that generate two dimensional chains of layout devices, by retrieving the schematic orientation of schematic devices in a symbolic view, and abutting the layout devices based on the schematic orientation such that the two dimensional chains of the layout devices maintain the schematic orientation. More specifically, EDA systems and methods disclosed herein may separate the layout devices into different sets, wherein each set may contain a particular type of layout devices. For example, a first set may contain photonic waveguides and a second set may contain radio frequency (RF) transmission lines. For each set of layout devices, the EDA systems and methods deterministically and iteratively traverse through the layout devices, abutting the devices using the schematic orientation, and creating one or more two dimensional chains of the layout devices.

Abstract: An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated, which may be performed by modifying the first MBIST logic(s). The first MBIST logic(s) may be modified based on a modification(s) to a register transfer level (RTL) list associated with the memory unit(s). A pattern control file or a Test Data Register mapping file may be modified based on the modification to the first MBIST logic(s).

Abstract: An exemplary bitmap file can be provided, which can include, for example, a map of a cell array structure of a memory(ies), a plurality of memory values superimposed on the cell array structure based on a simulated testing of the memory(ies). The memory values may be values being written to the memory(ies) while the memory(ies) is being tested. The memory values may be values in a test pattern(s) being used to test the memory(ies). Each cell in the cell array structure can have a particular memory value superimposed thereon. A cell(s) in the cell array structure may be highlighted, which may correspond to an incorrect memory value.

Abstract: Disclosed herein are embodiments of systems and methods for a deterministic modeling of integrated clock gate (ICG) activity in a vectorless power analysis of a synthesized integrated circuit (IC) design. The systems and methods may generate a priority list of the ICGs based on the slack values of the outputs of the ICGs calculated from a static timing analysis (STA). The system and method may further receive one or more priority inputs from the user and select the ICGs to be activated during power analysis based on the priority list and the priority inputs from the user. The systems and methods may propagate a set of state stimuli through the output cones of the selected ICGs and calculate the current through and power consumed by circuit devices in the output cones based on the state propagation and global data activity.

Abstract: Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions responsive to compiling a netlist file. The method further includes storing, by the compiling processor, a set of execution instructions into an instruction memory of an execution processor. The method further includes generating, by a compiling processor, a set of one or more keephot instructions for the execution processor based upon the set of execution instructions stored into the instruction memory of the execution processor. The method further includes storing, by a compiling processor, the set of keephot instructions into the instruction memory of the execution processor.

Abstract: Aspects of the present disclosure include a dual path phase locked loop (PLL) circuit with a switched capacitor filter topology along with systems, method, devices, and other circuits related thereto. The dual path PLL circuit includes an integral path and a proportional path. Both the integral path and proportional path include a charge pump and a loop filter. The outputs of a phase frequency detector (PFD) are sent to both charge pumps. The output of the integral path charge pump is connected to a capacitor, and the voltage on capacitor is used as the integral path control voltage for a voltage-controlled oscillator (VCO). A switched capacitor network is connected to the output of the proportional path charge pump and used to generate the proportional path control voltage for the VCO. Together, the two control voltages dictate the VCO's output frequency.

Abstract: Computer system for programmable built-in self-test (PMBIST) insertion into system-on-chip designs comprising one or more memories, including at least one processor and computer-executable instructions that cause the system to determine a PMBIST configuration based on one or more test configuration files; generate one or more package files based on the PMBIST configuration; insert PMBIST hardware into the SoC design based on the package files and characteristics of the memories; suspend PMBIST hardware insertion after an event related to the package files; and resume PMBIST hardware insertion after receiving one or more updated package files. In some embodiments, the package files are independent of vendor-specific memory models. In some embodiments, the package files comprise a plurality of data structures. Exemplary methods and computer-readable media can also be provided embodying one or more procedures the system is configured to perform.

Abstract: The present disclosure relates to a computer-implemented method for simulating a circuit design having a discrete domain segment connected to a continuous domain segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the discrete domain segment and the continuous domain segment. The method may also include splitting the discrete domain segment into a plurality of transistor network models to provide for bi-directional transfer of data between the continuous domain segment and the discrete domain segment, wherein at least one of the plurality of transistor network models utilizes only one or more drivers external to a module.

Abstract: Disclosed are techniques for implementing physics aware model reduction for a design. These techniques identify a design model and generate a first set of solutions with a first discretization scheme and a plurality of inputs. A second discretization scheme may be generated at least by performing geometry simplification and re-discretization based in part or in whole on one or more distributions from the first set of solution. With the second discretization scheme, a second set of solutions may be generated with the second discretization scheme and the plurality of inputs.