Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.

Abstract: Disclosed are techniques for implementing graph-driven verification and debugging of an electronic design. These techniques identify a pair of interest that comprises a target signal and a clock cycle or an event associated with the target signal from a verification or simulation result of an electronic design or a portion thereof. A boundary for relevant driver identification (RDI) operations may be identified for normal termination of the performance of one or more RDI operations. A debug graph may then be generated and stored at least by performing one or more RDI operations for at least the pair of interest based in whole or in part upon the boundary for RDI operations.

Abstract: Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such symmetrically balanced clock-tree ensures that a clock-signal reaches all of the clock-sinks simultaneously or near simultaneously thereby minimizing clock-skew across the clock-sinks. The minimal skew symmetric clock-distribution H-tree may therefore be used for higher performance and high speed ICs.

Abstract: An approach is described for implementing a GUI that provides a user interface for reviewing and correcting design rule violations within a CAD program. According to some embodiments, a user may enter a serial review process which may utilize contextual information to determine where to start that review process. Further, the serial review process may enable the user to review rule violations in an individual manner for a respective object. Furthermore, a dynamic directional violation identifier may be used to identify additional errors in the direction of movement, such as by processing a set of rules and parameters with respect to objects in the direction of movement. The serial review process and the dynamic directional violation identification may be combined in a single process such that as violations are reviewed, and corrections are attempted, they may be verified to determine if they generate additional violations.

Abstract: A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.

Abstract: Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. This information is then accessed in other embodiments, and scaled to generate scaled timing values describing the statistical timing characteristics of a circuit element or block estimated from the skew-based values. These values may then be used for further timing analysis.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing clones for an electronic design. These methods and systems identify a schematic design of an electronic design and a set of cloning rules, configurations, or settings for implementing clones for the electronic design. These methods and systems then generate a plurality of synchronous clones in a layout of the electronic design based in part or in whole upon the set of cloning rules, configurations, or settings, without parsing the electronic design or a portion thereof.

Abstract: The time to test integrated circuits is increasing as a function of the complexity of integrated circuits and processes used to fabricate the integrated circuits. Embodiments of this disclosure include systems and methods for reducing the time to integrated circuits by reducing the number of devices individually modeled. Embodiments can reduce the number of modeled devices by combining two or more devices into a single combined device that models all discrete devices, but in a reduced form.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies. These techniques identify a schematic design and a layout having at least one virtual hierarchy of an electronic design. These techniques then implement an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout. These techniques further check the figure group based in part or in whole upon one or more criteria and update one or more data structures for the at least one virtual hierarchy and the figure group based in part or in whole upon the ECO.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a floorplan with virtual hierarchies and figure groups for an electronic design. These techniques identify a plurality of layout circuit component designs in a layout and identify or create a figure group at a virtual hierarchy for the plurality of layout circuit component designs. The figure group can be modified into a modified figure group in response to a request for a modification of the figure group. At least one layout circuit component design of the plurality of layout circuit component designs can then be reinstalled into the modified figure group to fulfill the request for modification of the figure group.

Abstract: Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.

Abstract: A system and method are provided for adaptively optimized recomposition of a parts list for fabrication of an electronic circuit product. A parts list acquisition portion forms a parts list containing a plurality of constituent parts entries read from one or more predetermined sources. The parts entries are respectively identified in the parts list by different corresponding part identifiers. An optimization unit coupled to the parts list acquisition unit comparatively determines mutual matching between different parts entries based on at least one optimization parameter. The optimization unit intermediately recomposes the parts list by incorporating one or more suggested parts substitutions to adaptively consolidate mutually matched pairs of parts entries.

Abstract: Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for all instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

Abstract: A system and method are provided for controlling access to memory to support processing of a master control operation. A data control portion is configured to carry out a plurality of data access operations on the memory device, including read, write, and read-modify-write operations for selectively addressed storage locations defined in the memory. An error control portion executes to detect error in a data segment as stored in the memory. The error control portion corrects a data segment read from the memory device for at least one type of detected error. A command control portion generates commands for actuating the data access operations of the data control portion. The command control portion includes a corrective writeback unit executable responsive to detection of correctable error in a data segment to actuate a read-modify-write operation to the data segment's storage locations. The corresponding storage locations of the memory are thereby adaptively scrubbed.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design environment including both a design under test (“DUT”) and a testbench. Embodiments may further include simulating an electronic design associated with the electronic design environment and generating a coverage database associated with the electronic design. Embodiments may include performing coverage analysis of the DUT and testbench using an automated inheritance aware analysis and applying the coverage analysis results to the testbench after simulation.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. The method may include receiving, using a processor, an electronic design at a verification environment and generating a symbolic constant for use with the verification environment. The method may further include identifying a plurality of X sources associated with the verification environment and modifying the plurality of X sources based upon, at least in part, the symbolic constant. The method may also include running a first target node and if the first target node is proven, run at least one additional target node until all target nodes are proven.

Abstract: The present disclosure relates to a system and method for performing Path-Based Analysis (PBA) of an electronic circuit design. Embodiments may include receiving a command to create a spice deck of a timing path associated with the electronic circuit design. In response to receiving the command, embodiments may further include initiating PBA for the timing path and identifying one or more stages within the timing path. Embodiments may also include performing a delay calculation for each of the one or more stages and generating a stage spice deck for each of the one or more stages based upon, at least in part, information from the delay calculation, wherein the stage spice deck encapsulates all elements of the stage. Embodiments may further include connecting the stage spice deck for each of the one or more stages in series to form a complete path spice deck.

Abstract: Disclosed herein are systems and methods to reduce wirelength and congestion in an integrated circuit (IC) design. The systems and methods disclosed herein may be implemented during a detailed placement stage of IC design to identify and select a cell for relocation and determine an area of interest to which the cell can be relocated. The systems and methods may identify one or more potential locations within the area of interest where the cell can be relocated to, and then determine a cost based upon the wirelength and/or congestion for the selected cell, at each of the one or more potential locations. Upon determining that a potential location may have a lower cost compared to the original location of the selected cell, the systems and methods may relocate the selected cell to the potential location.

Abstract: A system, method, and computer program product for automatically managing control configurations in an application graphical user interface (GUI). Interface element specifications may be configured via a customized overlay file corresponding to at least one party having influence over the application controlled by the GUI, such as an application vendor, a user group, and an individual user. The overlay file is created and saved via an interface manager GUI that allows new interface elements such as toolbars and toolbar buttons to be added, and existing interface elements to be modified, but does not allow existing default interface elements to be destructively edited, only hidden or visibly disabled. The overlay file is processed during program environment startup and when user actions trigger a separate application or feature window activation or reset a particular overlay file's modifications. Compatibility with vendor-supplied default interfaces and other overlay file based customizations is maintained.

Abstract: An improved approach is provided to identifying the boundary of data encoded using additive cyclic codes. In some embodiment, the process includes determining a first calculated parity of a first bit stream window, and, second, one or more updates to the calculated parity of the bit stream window to determine the parity of the next bit stream window, where after each update to the calculated parity, the calculated parity is compared with the target parity, and matching the calculated parity to the target parity indicates a proper boundary of a bit stream window. In some embodiments, the process supports shortened cyclic codes. In some embodiments, the bit stream boundary can be identified prior to descrambling the bit stream inputs for a given bit stream window. In this way, the process can avoid unnecessarily descrambling of the bit stream windows that are not properly aligned to a bit stream boundary.