Patents Assigned to Cadence Design Systems, Inc.
  • System and method for tuning a graphical highlight set to improve hierarchical layout awareness and editing
    Patent number: 10223495
    Abstract: The present embodiments relate generally to integrated circuit design, and more particularly to techniques for providing enhanced visual information about a shape of interest in a hierarchical design. For example, embodiments relate to automatically and dynamically creating or adjust a highlight set in a graphical user interface for providing hierarchical information about shapes in a hierarchical design in a more productive manner, and possibly concurrently with other textual information about shapes that is being displayed. In these and other embodiments, these automatic and/or dynamic highlight sets can be based on the relationship between a current cursor position and shapes of a hierarchical design that is currently being edited using a GUI of a layout editor tool that is adapted with the functionality of the present disclosure.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 5, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sunil Agrawal, Devendra Deshpande
  • Spice model bin inheritance mechanism
    Patent number: 10223484
    Abstract: A system, method, and computer program product for facilitating model binning in circuit simulators. Embodiments enable specification of models spanning binning dimensions, such as device width and length, in a model group via inheritable model bins. New simulator modeling syntax and semantics eliminate much of the redundancy and parsing overhead from model parameter specifications in foundry process design kits. Indirect and optional inheritance is also enabled, allowing for fine grain and coarse grain grids in the same model group.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 5, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Donald J. O'Riordan, Richard J. O'Donovan, Saibal Saha, Jushan Xie
  • Constraint validation process
    Patent number: 10216888
    Abstract: The present disclosure relates to a system and method for constraint validation in an electronic design. The method may include receiving an electronic design at an electronic design automation application and analyzing at least a portion of the electronic design at a constraint validation tool configured to analyze one or more physical constraints in a design layout associated with the electronic design. The method may further include applying one or more programmable electrical rule check (“PERC”) rules and one or more constraints to the electronic design, wherein the one or more PERC rules are configured to perform one or more electrical rule checks.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: February 26, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mikhail Kanshin, Andrey Freidlin, Alexey Kalinov, Andrei Savelev, Douglas M. Den Dulk, Wojciech Wojciak
  • Systems and methods for power efficient flop clustering
    Patent number: 10216880
    Abstract: Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a load-balancing process. In another embodiment, the methods use a local cleanup process to rewire the nodes between neighboring clock buffers to further reduce the amount of clock-gaters.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: February 26, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Zhuo Li, Charles Alpert, Brian Wilson
  • Methods, systems, and computer program products for implementing an electronic design with time varying resistors in power gating analysis
    Patent number: 10216887
    Abstract: Various embodiments implement an electronic design with power gate analyses using time varying resistors. Design data of an electronic design or a portion thereof may be identified at an electronic design implementation module. First stage electrical characteristics may be generated at least by performing a first stage electrical analysis on a reduced representation of the electronic design or the portion thereof. Second stage electrical characteristics may further be generated at least by performing a second stage electrical analysis on a parasitic injected representation of the electronic design or the portion thereof with a time-varying model for the power gate. The electronic design or the portion thereof may then be further implemented based in part or in whole upon the one or more electrical analyses or simulations.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 26, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: John Yanjiang Shu, Wei Michael Tian, Richard J. O'Donovan
  • System and method for implementing and validating star routing for power connections at chip level
    Patent number: 10210301
    Abstract: A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Such pathways are routinely required for power and signal distribution purposes. Automated scripts perform a star routing methodology and validate the routing results. The methodology processes input width and layer constraints and from-to's denoting start and end points for each route by invoking a star_route command in a router that implements interconnections as specified. Routing results are validated by checking for routing violations, including shared segments and width violations. Violations are marked for correction.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 19, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ankur Chavhan, Devesh Jain, Behnam Farhat, Andrey Freidlin, Sundararajan Shanmugam, Susan Zueqing Zhang
  • Methods, systems, and computer program product for dynamically abstracting virtual hierarchies for an electronic design
    Patent number: 10210299
    Abstract: Disclosed are methods, systems, and articles of manufacture for dynamically abstracting virtual hierarchies for an electronic design. These techniques identify at least a portion of a layout of an electronic design and a virtual hierarchy in the layout portion according to a value for a display stop level. A plurality of figure groups at one or more virtual hierarchies in the layout portion may also be identified in the layout portion. These techniques select a plurality of layout circuit component designs according to the virtual hierarchy. The layout portion may then be abstracted into an abstracted layout portion at least by displaying the plurality of layout circuit component designs and suppressing one or more remaining layout circuit component designs.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 19, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Ginetti
  • Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques
    Patent number: 10204201
    Abstract: Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Lawrence Loh, Artur Melo Mota Costa, Breno Rodrigues Guimaraes, Fabiano Peixoto, Andrea Iabrudi Tavares
  • Method and system for implementing data reduction for waveform data
    Patent number: 10204187
    Abstract: An improved approach is provided to generate and display waveform data, where data reduction is intelligently applied to create filtered waveform data. By reducing the quantity of the waveform data in an intelligent manner, this permits the waveform display tool to process the waveforms quickly enough for interactive usage, while still retaining sufficient data fidelity for accurate data analysis and waveform visualization.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Iain Farquharson
  • Methods and systems for implementing high bandwidth memory command address bus training
    Patent number: 10203875
    Abstract: A method to initiate Command Address (CA) training on High Memory Bandwidth is provided to optimize CA bus setup and hold times relative to the memory clock. HBM protocol does not define any way to support CA training, but defines a very high working frequency. The high frequency makes it very difficult to ensure the timing on CA Bus-Row/Column command bus and CKE. As such, executing CA training before any normal operation is necessary to ensure the best setup/hold timings. The CA training takes advantage of protocol based instructions to initialize and implement CA training.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Guangxi Ying, Zhehong Qian, Liang Huo, Yanjuan Zhan
  • Method, system, and computer program product for implementing electronic designs with automatically generated power intent
    Patent number: 10204180
    Abstract: Various embodiments implement an electronic design with automatically generated power intent. One or more inputs to a physical electronic design implementation module may be identified for power intent generation for an electronic design. The power intent for the electronic design may be generated by using at least one or more power related characteristics that are determined from at least the one or more inputs for the power intent generation. With the generated power intent, the electronic design may be implemented at least by guiding the implementation of the electronic design with at least the generated power intent while reducing usage of one or more computing resources.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kai-Ti Huang, Pinhong Chen, Richard M. Chou
  • Relocate targets to different domains in an emulator
    Patent number: 10198538
    Abstract: The embodiments described herein may improve utilization of an emulator system's resources, and may improve efficiency and effectiveness in bug-identification and/or target-debugging; the components described herein may improve utilization of the emulator's resources, reduce wait time to execute emulation routines, and may limit or eliminate the need to stop or kill emulations in process. The various embodiments described herein allow for dynamically associating domains and targets by dynamically allocating and assigning domains with particular target connections, which are pins and/or wires that connect target pods to the emulation system. An emulation system may comprise one or more target MUXs that are situated between the target connections and the domains, to allow the relationships between target pods and domains to be identified and switched dynamically.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Barton Quayle, Mitchell G. Poplack, Sundar Rajan, Chuck Berghorn
  • Systems and methods for dynamic RTL monitors in emulation systems
    Patent number: 10198539
    Abstract: Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tsair-Chin Lin, Jingbo Gao, Alon Kfir, Long Wang, Wei Zeng, Zhao Li
  • Clock cell library selection
    Patent number: 10198551
    Abstract: Systems, methods, media, and other such embodiments described herein relate to trimming cell lists prior to generation of a routing tree for a circuit design. One embodiment involves accessing a cell library including cell data and a cell list for a plurality of cells. Specialized delay cells are removed from the cell list, and remaining cells are analyzed to identify a set of cell characteristics. Cells are then trimmed from the cell list based on comparisons between the cell characteristics of the remaining cells. If certain cells are sufficiently similar, secondary characteristics can be used to further trim the cell list. The trimmed cell list can then be used to generate a routing tree for the circuit design according to associated design criteria.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amin Farshidi, Zhuo Li, Charles Jay Alpert, William Robert Reece
  • System and method for profiling during an electronic design simulation
    Patent number: 10198540
    Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation using a profiler. The method may include simulating, using a computing device, an electronic design associated with a programming language. The method may further include recording a first time corresponding to a first user-defined point in the simulation. The method may also include recording a second time corresponding to a second user-defined point in the simulation. The method may further include determining a difference in time between the first and second times and displaying a visualization including at least one of the first time, the second time, a value of a variable at the first time, a value of the variable at a second time, and the difference in time.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 5, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Daniel Asher Cohen
  • Generating and inserting metal and metal etch shapes in a layout to correct design rule errors
    Patent number: 10192021
    Abstract: Embodiments relate to physically implementing an integrated circuit design while conforming to complex design rule constraints. According to some aspects, embodiments relate to an automated method for generating shapes for correcting design rule errors such as line end-to-end spacing violations. In these and other embodiments, the automated method determines the errors post-placement and automatically generates the required shapes, taking into account additional process design rules and neighboring shapes. Some embodiments consider clusters of objects, potential legal areas between line-ends, merging of potential legal areas and generation of various shapes to produce a design rule correct layout.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 29, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Satish Raj, Ying-Hui Wang, Joyjeet Bose, Sachin Shrivastava
  • Methods, systems, and computer program product for implementing dynamic maneuvers within virtual hierarchies of an electronic design
    Patent number: 10192020
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing dynamic maneuvers within virtual hierarchies of an electronic design. These techniques identify or generate a plurality of figure groups at one or more virtual hierarchies in a layout portion and receive a request to descend into or ascend from a figure group at a virtual hierarchy of the one or more virtual hierarchies. In response to the received request, these techniques update a layout view into an updated layout view at least by exposing layout design details in the figure group for native editing according to the request to descend into or ascend from the figure group and optionally synchronize a corresponding schematic design view according to the updated layout view.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Ginetti
  • Methods and devices for a memory interface receiver
    Patent number: 10193555
    Abstract: Embodiments relate to systems, methods and computer readable media to enable design and creation of receiver circuitry One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, a first N-type metal oxide semiconductor (NMOS) field effect transistor (FET), a second NMOS FET, a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET, and a complementary metal oxide semiconductor (CMOS) logic gate. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Eric Harris Naviasky, Thomas Evan Wilson
  • Method and system for implementing efficient trim data representation for an electronic design
    Patent number: 10192018
    Abstract: An improved approach is described to implement trim data representation for an electronic design. Instead of maintaining a gap shape object for every gap in the layout, existing objects adjacent to the gap location are configured to include attributes of the gap shape. The properties of the gap shape can then be derived from the adjacent objects.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vassilios C. Gerousis, Shane Zhang, Jianmin Li, Stefanus Mantik, Louis Tsai
  • Test logic at register transfer level in an integrated circuit design
    Patent number: 10192013
    Abstract: Electronic design automation (EDA) systems, methods, and computer readable media are presented for adding design for test (DFT) logic at register transfer level (RTL) into an integrated circuit (IC) design at RTL. In some embodiments, the DFT logic at RTL includes a port that connects to a hierarchical reference with a hierarchical path in the tree structure hierarchy to a part of the IC design at RTL. Such DFT modification helps to decrease the number of new ports added at this stage, and as a result assists subsequent debugging and back-annotation of RTL.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: January 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Puneet Arora, Ankit Bandejia, Navneet Kaushik, Steven Lee Gregor