Abstract: Methods and computer-readable media for effecting physically efficient scans of integrated circuit designs may include selecting a two-dimensional grid size for exposure to the method, the two-dimensional grid having a size that includes a first side length, a second side length, and a number of flops. The method is performed to select a two-dimensional grid size that maximizes compression efficiency and limit wiring congestion on the IC. In one aspect, the method may be performed on each region of the grid that maintains one of a respective first side length and a respective second side length greater than one, including selecting a larger side, determining if the larger side is odd or even, and dividing the grid along the larger side into two regions each having a proportion of the flops. The scans of the resulting regions are efficient, and consequently facilitate integrated circuit design and subsequent manufacture.

Abstract: Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.

Abstract: The present disclosure relates to a computer-implemented method for transient simulation of an input/output buffer model. The method may include generating an input/output buffer data file associated with a first model of an electrical circuit. The method may also include determining at least one of a node voltage and a branch current associated with the electrical circuit using, at least in part, a latency insertion method, the method may further include performing one or more simulations on a second model of an electrical circuit, the one or more simulations incorporating, at least in part, the input/output buffer data file and the latency insertion method.

Abstract: Disclosed are mechanisms for implementing an IC package layout design with an integrated circuit package design estimator. These mechanisms determine an estimated number of layers for an integrated circuit (IC) package design including one or more IC die designs, determine whether the estimated number of layers suffice to accommodate routing demands for the IC package layout design, determine a power layer and/or a ground layer based in part or in whole upon one or more factors, and generate an output for the IC package layout design based using at least the estimated number of layers and the power layer and/or the ground layer. These mechanisms use input including connectivity information, thermal effects, and/or IC placement information to determine estimates for the total number of layers, layer stack-up, power and ground plane assignment, and via libraries to guide IC package layout design.

Abstract: A system and method are provided for efficient allocation of data in a memory array having regions of varying storage reliability. Storage locations for bands of data are selectively allocated in a manner which evenly distributes the probability of error in the data when stored in the memory array in spite of the varying storage reliability. A distribution controller is provided to effect such distribution of data to maintain a collective error rate of each data band within a preselected or predetermined range. The system and method also generally provide for storing at least a first and a second data band in different corresponding sets of storage channels. The system and method also generally provide for at least one of the data bands being stored in regions of differing reliability across the set of storage channels therefor.

Abstract: Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.

Abstract: A full wave rectifier (270) for use as part a differential signal detector (400) detects both high and low envelopes of differential signals (RXa, RXb) at a pair of differential inputs (202, 204) and provides a sense signal (VSENSE) at an output (220) thereof. The differential signal detector (400) includes both the full wave rectifier (270) and a voltage reference source (260) having a circuit architecture in common, and a comparator for comparing the sense signal (VSENSE) with a reference voltage (VREF). The circuit configuration of both the full wave rectifier (270) and the voltage reference source (260) include first and second differential input circuits (271 and 273, 261 and 263) each including a pair of field effect transistors (2722, 2742 and 2762, 2782; 2622, 2642 and 2662, 2682) of different conductivity type having respective source terminals (2728, 2748; 2768, 2788; 2628, 2648; 2668, 2688) coupled together.

Abstract: This document discusses, among other things, systems and methods to access n consecutive entries of a register file in a single operation using a register file entry index consisting of B bits, wherein B is less than the binary logarithm of a depth of the register file, which corresponds to the number of entries in the register file, and to automatically select, for a set of register arguments for the n consecutive entries, between a register port for each argument requiring a register port or one or more shared register ports for the set of register arguments according to description of an instruction set architecture associated with the register file.

Abstract: A system and method are provided for selective bit-wise masking of X-values in scan channels in an integrated circuit (IC) during a built-in self test (BIST). The composite mask pattern is selectively generated according to locations of X-values identified in a simulation of the IC. The composite mask pattern is stored on the IC and cyclically maintained while being applied to the operational scan results of the IC. The composite mask pattern is recycled over a plurality of scan iterations to effectively prevent the X-values from influencing the resulting signature of the BIST that represents a functional fingerprint of the IC and minimize storage requirements for the composite mask pattern.

Abstract: In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.

Abstract: A system and method are provided which incrementally samples and delays a signal passed through a transmission channel thereto. A receiver section is provided with a delay stage including a sample storage portion having a plurality of capacitors. A switch portion selectively switches the capacitors to respectively store incremental samples of the signal received through the channel. A clock source is provided to generate a plurality of periodic clock signals progressively shifted by a predefined clock phase increment. The clock source drives the switch portion to synchronously cycle the capacitors through at least sample and readout modes of operation, which are mutually offset in time by a preselected number of clock phase increments. The received signal is collectively reconstructed from the incremental samples of the capacitors, such that the reconstructed signal is delayed by the preselected number of clock phase increments.

Abstract: In order to detect and locate defects, or faults, in a plurality of chips or other circuits sharing a common design, said chips are each tested for incorrect outputs, or failures, in response to inputs. The incorrect outputs are then collectively diagnosed in a single simulation by simulating a series of suspected fault candidates on a simulated chip of the chip design, and afterward comparing the incorrect outputs generated by each fault candidate to the incorrect outputs of the individual chips, to determine if a fault candidate generates all failures for a chip and no others. The test inputs and expected outputs may be predetermined through Automatic Test Pattern Generation. The fault candidates may be determined by use of a backtrace process such as back cone tracing. The failures may be recorded in association with a measure point, the input pattern that resulted in the failure, and the failure value.

Abstract: Methods and systems for interconnecting circuit components with track patterns are disclosed. The method identifies a source pin on a first track and a destination pin on a second track and determines a third track in a different routing direction based on design rules governing track patterns. The method further determines a transition pattern for the interconnection between the source pin and the destination pin by using at least the third track. The method may use one or more dummy pins or ordering of pin connections in implementing the interconnection to satisfy certain design rules. The lengths of some wire segments of the interconnection may be further adjusted to satisfy certain design rules. Compaction may be performed to have two wire segments share the same track while the lengths or widths of one or both wire segments may be further modified to ensure design rule compliance.

Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.

Abstract: A method and system are provided for profiling data packets as they flow along a datapath in a device under test to locate and debug problems with the datapath or the individual nodes constituting the datapath to thereby expedite formal verification of a device under test and resolve any problems found.

Abstract: Methods and systems for implementing repetitive track patterns for electronic designs are disclosed. The method determines a track pattern within a period and repeats the track pattern for a number of times to form repetitive track patterns. Compliance with photomask designation design rules and track pattern design rules by both the track pattern and the repetitive track patterns is maintained by adding one or more intermediate tracks. A track may be added or removed from the track pattern or replaced by another track associated with a different width by using one or more intermediate tracks. The method may validate a period and replace an invalid period with a valid period. During the identification of the tracks in a track pattern for constructing repetitive track patterns, the method also forward predicts a predetermined number of tracks or predicts one or more tracks for a predetermined distance.

Abstract: A model checking tool, which is used to test a circuit design, attempts to reach a target state from an initial state in the state-space of the circuit design using one or more intermediate states. Through an iterative process, the tool identifies intermediate states in the state-space of the circuit design that are used to generate starting states for subsequent iterations of the process. The intermediate states help to restrict the scope of the state-space search to reduce the time and memory requirements needed to reach the target state. The model checking tool also explores the state-space in parallel from a subset of computed restart states, which reduces the possibility of bypassing any essential intermediate or target states.

Abstract: One aspect identifies an interconnect and associated design rule(s) and moves a portion of the interconnect to an adjacent track by using a spreading process on a one-dimensional design data based on the design rule(s) to determine whether the interconnect including the moved portion provides a DRC clean implementation. This aspect examines an interconnect in its entirety without being confined within a prescribed boundary of a fixed region in the layout. The one-dimensional design data provides expedient runtime and may be converted back into two-dimensional form for the layout. Another aspect iterates through multiple spreading distances to route or modify interconnects in a layout by performing multiple Boolean operations on the interconnect and adjacent shape(s) to determine the final form of the newly created or modified interconnect complying with various design rules.

Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, using at least one computing device, an electronic design. The method may also include associating, using the at least one computing device, an identifier with each constraint solver call utilized in a simulation of the electronic design. The method may also include generating, using the at least one computing device, an application programming interface configured to allow a user to navigate through electronic design simulation results based upon, at least in part, the identifier associated with each constraint solver call.

Abstract: Disclosed are various embodiments relating to methods, systems, and articles of manufacture for using multiple modes during execution of a program. Various embodiments enable a use to switch among multiple modes of execution of a program during an execution of the program without recompiling a higher level code of the program or without restarting the execution of the program from the beginning. Some embodiments enable the user to switch among different modes regardless of whether or not the preparation for the execution of the program in modes other than the first mode is available. Some embodiments enable the user to switch among different modes of execution of a program while sharing the same environment or context of the execution of the program among these different modes of execution.