Abstract: Disclosed is an improved approach to implement timing signoff and optimization. Integrated MMMC timing closure functionality is provided in a single software session. The system provides the capability to perform signoff analysis, debugging, ECO, and TSO optimization for a large number of MMMC views in single software session.

Abstract: Various mechanisms and approaches identify multiple cells in an electronic design and multiple sets of stall prevention requirements or multiple sets of transactions for the multiple cells and determine dependencies between stall prevention requirements. A graph is constructed to represent the dependencies and the stall prevention requirements or the transactions involved in the dependencies by using the stall prevention requirements or the transactions as the nodes and the dependencies as the arcs connecting the nodes in the graph. One or more loop analyses are performed on the graph to identify one or more loops as one or more potential deadlocks. False deadlocks may be eliminated from further processing. The analyses and deadlock detection may be independently performed for each cell in sequence or in parallel to divide and conquer a complex electronic system design.

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more processors, an electronic design and visually displaying a plurality of possible route sets associated with the electronic design at a graphical user interface. The method may include providing an option to select between the plurality of possible route sets at the graphical user interface.

Abstract: The present disclosure relates to a system and method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include recording, at a client computing device, a plurality of operations associated with an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include generating a script based upon, at least in part, the recorded operations and displaying, at the client computing device, at least a portion of the generated script.

Abstract: The present disclosure relates to a system and method for determining an effective electrical resistance in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design and identifying one or more features associated with the electronic circuit design. Embodiments may also include performing a resistance only extraction of a circuit net associated with the electronic circuit design and identifying at least two node locations from the electronic circuit as one or more port nodes. Embodiments may further include reducing the resistance only extraction to an equivalent circuit including only the port nodes and attaching a high-resistance ground voltage source to at least one of the port nodes of the reduced equivalent circuit. Embodiments may also include generating a conductance matrix, based upon, at least in part, the reduced equivalent circuit.

Abstract: A method and system are provided for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design. A circuit editing tool electronically renders schematic representations of circuit objects responsive to user input. A layout object acquisition unit coupled to the circuit editing tool actuates responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit objects for generating a corresponding layout object. The predetermined layout strategy includes a defining set of placement and interconnection routing schemes for the grouped circuit objects, one relative to the other. A layout object management unit coupled to the layout object acquisition unit and circuit editing tool adaptively reconfigures the layout object in accordance with the layout strategy thereof responsive to an editing operation being imposed on at least one circuit object within the layout object.

Abstract: A computer implemented method for performing floating point operations as part of a processor architecture that also includes fixed point operations is disclosed. The computer implemented method includes providing a group of instructions within the fixed point architecture. A floating point value is split between two programmer visible registers. In a system and method in accordance with the present invention a new form of floating point representation and associated processor operations, including efficient complex number representations and operations are utilized.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing an electronic design including, at least in part, one or more hardware description languages and one or more software programming languages. Embodiments may further include calculating configuration information without analyzing the electronic design, wherein the configuration information includes one or more memory elements configured to control a mode of operation of the electronic design. Embodiments may also include determining a change in the one or more memory elements and altering a function associated with the electronic design verification based upon, at least in part, the determined change.

Abstract: Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a serializer-deserializer in conjunction with a second XOR decompressor in a second stage.

Abstract: An improved approach is provided to implement equivalency checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis. Instead, the two designs are checked to see if they are equivalent on the transaction-level. This approach abstracts the timing delays between the two designs, which allows verification of data transportation and transformation between the designs.

Abstract: Various embodiments scalable statistical library characterization for electronic designs by identifying an electronic design, performing circuit simulations on strongly connected components on a component-by-component basis, performing the logic cone analysis on the entire electronic design, and performing combinations of influences on the electronic design caused by variations of parameters. Some embodiments perform simulations on one or more stronger parameters or the strongest parameter of a circuit component and use the simulation results to calibrate the predicted behaviors of one or more remaining circuit components of the electronic design. Various statistical or mathematical techniques may be used for performing the combinations of influences on the electronic design caused by variations of parameters. The techniques described are scalable with the increase in complexities and sizes of electronic designs while reducing or minimizing the impact on sensitivity accuracy.

Abstract: Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation capacitor. One embodiment is high speed level translation memory driver apparatus comprising a plurality of field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) logic gates to drive the FETs, and a voltage translation capacitor with a first terminal of the voltage translation capacitor connected to an output of a second CMOS logic gate and a second terminal of the voltage translation capacitor connected to a gate terminal of a first P-type FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.

Abstract: A system, method, and computer program product for viewing analog simulation check violations in an EDA framework. Embodiments combine input data tables into a single data table for each check type using SQL inner join operations, create a SQL view of the single data table to list individual check violations, and output the view for user inspection of the corresponding check violations. Embodiments normalize the input data tables to include details of circuit nodes, elements, and paths implicated in the check violations. Additional views combine views of different check types into unified summary tables. Embodiments create a second view to aggregate individual check violations that involve the same circuit objects over time, and output the second view. Output views are self-describing, to enable a single graphical user interface to operate across multiple simulator versions. Metadata tables describe data types presented in various view columns, and user interactions allowed therewith.

Abstract: Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints and correlation between STA results and SPICE results. Methods and systems of the present disclosure find application in, among other things, timing signoff in an electronic design and verification process.

Abstract: A computer implemented method and system for providing a Fast Fourier Transform (FFT) capability to a fixed point processor architecture is disclosed. In a first aspect the computer implemented method and system comprises providing an instruction set within the fixed point architecture. The instruction set includes a plurality of instructions to calculate at least one set of add operations within a FFT butterfly. The plurality of instructions are controlled by a mode register, wherein a plurality of vector register files and a scratch state memory provide input data to at the at least one set of add operations.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: Accurate timing analysis during STA is performed using detailed waveform information in addition to the traditional slew information. A waveform memory system efficiently stores the detailed waveforms that are used in, calculated during, and propagated throughout timing analysis for a circuit design. During the STA process, for multiple modeled stages of circuit design, a waveform including information detailing the form of the waveform is compressed, stored in, decompressed, and retrieved from a memory system. The memory system provides for storage efficiencies including long-term and short-term storage areas, multi-level storage, and separate storage for each view evaluated during the STA.

Abstract: Methods and systems for checking or verifying shapes in electronic designs are disclosed. The method identifies a dictionary (if pre-existing) or determining the dictionary by creating the dictionary and reduces dimensionality of design data by using a sliced line. Shapes are transformed into sliced line segments along the sliced line. Dictionary entries for shapes are associated with corresponding sliced line segments, and the design is checked or verified using the sliced line segments and the associated dictionary entries rather than using two-dimensional shapes or geometric data. Sliced line segments may be further partitioned or merged. Non-conforming shapes corresponding to no tracks of track patterns are identified and determined whether violations of design rules or requirements may be resolved by one or more other shapes using the corresponding sliced line segments.

Abstract: A system and method for providing a scalable server-implemented regression query environment for remote testing and analysis of a chip-design model receives chip-design information, including the chip-design model to be tested and one or more attributes for testing the chip design model; receives a first regression simulation test request from the client-side integration client; initiates a proxy instance for a first regression simulation test to be executed by an application programming interface (API), based on the first regression simulation test request; selects, by the API, the attributes for testing the chip-design model; executes, by the API, the first regression simulation test on the chip-design model using the selected attributes; monitors, by a server-side database manager, the first regression simulation test during execution of the first regression simulation test; and stores, by the server-side database manager, one or more results of the first regression simulation test in a database.

Abstract: Methods, systems, and computer readable media are disclosed for simulating a circuit. The method may comprise a step of providing a network model of the circuit having a plurality of ports, the plurality of ports being associated with one or more net pairs. The method may also comprise combining the plurality of ports into one or more groups based on the net pairs, each group corresponding to a net pair. In addition, the method may comprise calculating, for each group, one or more expansion elements, wherein the one or more expansion elements are associated with a shared property among all ports of the group. Moreover, the method may comprise simulating the circuit using a combination of the expansion elements calculated for each group.