Abstract: Aspects of the present invention provide a system and method for a user of an event-driven simulator to specify complex breakpoint conditions and actions which allow both hardware and software states to be accessed. In a virtual platform modeling hardware components, bare-metal software programs, and high-level software applications or processes, a global identifier may be used to unambiguously identify each element, object, and subcomponent of the modeled system. The unambiguous global identifier may include an instance name and a hierarchical path name. A state of a specific element, object, or modeled component may trigger a breakpoint or be utilized or set as part of a breakpoint condition.

Abstract: Disclosed is a method, system, and computer program product for automated implementation of pipeline flip-flops in an electronic design. Two operating modes can be used either together or separately to implement pipeline flip-flops. An analysis mode is employed to perform a determination of the number of stages of pipeline flip-flops needed for particular portions of an electronic design. A placement stage is used to place the pipeline flip-flops in the layout.

Abstract: Aspects of the present invention describe a system and method for a user of an event-driven simulation environment and/or embedded software debugger interface to step through the source code of components modeled by the environment/debugger, including the embedded software or hardware model source code. In a virtual platform modeling hardware components, bare-metal software programs, and high-level software applications or processes, the source code of each modeled component may be stepped through during simulation. Insertion points for breakpoints or watchpoints may be detected during a traversal of the source code of each component being modeled in the virtual platform and such breakpoints inserted automatically.

Abstract: Some embodiments provide a method for automatically generating several design solutions that remedy a design rule violation committed by a set of shapes in an IC design layout. The method receives a marker that indicates the design rule violation and contains information about the violation. The marker in some embodiments can be rendered as a geometric shape in the IC design layout. Based on the marker, the method generates several solutions each of which will cause the set of shapes to meet the design rule when the solution is applied to the set. Each solution requires moving at least one edge of a shape in the set of shapes.

Abstract: Methods and systems for implementing a microprocessor with a selective register file bypass network are disclosed. Late bypasses are removed from a register file bypass network of a microprocessor design. One or more late bypasses are then added back to the register file bypass network based at least in part upon the results of analyzing a plurality of instructions that are to be processed in an instruction pipeline of the microprocessor. An electronic design for at least the register file bypass network is then generated with these one or more late bypasses that are added to the register file bypass network. Without incurring additional hardware or cost for the microprocessor design, one or more bypasses in the register file bypass network may be optionally shared among multiple free-riders, and an entire port stage may also be optionally bypassed to another port stage based upon one or more criteria.

Abstract: One aspect creates or identifies a rule, identifies or creates track pattern(s), and associate the rule with the track pattern(s). The rule is used to guide physical implementation tools to implement electronic designs which not only satisfy the constraints of the rule but also the constraints of the track pattern(s). Some other aspects are directed at interpretation or automatic association or assignment of a layer constraint by determining whether a track pattern on a layer with a first rule matches a second rule, and adding the track pattern to the layer constraint for the second rule on the layer. Another aspect is directed at automatic creation of a rule by creating a new rule, examining each track pattern associated with a first rule, determining whether the new rule matches the first rule, and adding the track pattern to a layer constraint for the new rule.

Abstract: A system and method for managing SOA assertion violations and related simulator output. Embodiments transform simulator output into descriptive data regarding SOA violations for relational database storage and processing. The database executes queries on the descriptive data according to user input specifying particular descriptive data and SOA assertion violations of interest, and outputs query results for further user action. Individual and accumulative SOA violations are more easily explored by users, through a search language that facilitates selection rule specification via pre-existing or user-defined filters. Filters may inherit rules and combine them with logical and comparative operators, enabling easy construction of complex selection expressions to provide more intuitive design guidance.

Abstract: Disclosed are various techniques that check, verify, or test multi-fabric designs by receiving a request for checking correctness of a multi-fabric design across at least a first design fabric and a second design fabric. A request for action is transmitted from a first EDA tool session to a second EDA tool session. Connectivity information of second design data in the second design fabric is identified by the second EDA tool session in response to the request for action from the first EDA tool session. These various techniques then check the correctness of the multi-fabric design in the first design fabric by using at least the connectivity information of the second design data. A symbolic representation may be used to represent design data in an EDA tool session to which the design data are not native.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.

Abstract: One aspect interconnects two regions subject to different rules and using transition rule(s) in a transition region or cost mechanism(s), where these rules may include soft rule(s), hard rule(s), or combinations thereof. These two regions may reside on the same routing layer or on different routing layers. This aspect allows physical design tools to transition across gridded, gridless, tracked, or trackless regions subject to different rules on the same or different layers. Another aspect interconnects an object subject to the first rule(s) and the second rule(s), while the object satisfies or violates the first rule(s). These aspects use spacetile(s) on a spacetile layer as search probe(s) to find viable implementation solutions, although the spacetile(s) and hence the search probe may violate one or more rules. A spacetile layer may be identified or created for each rule and may be associated with relevant features subject to relevant rule(s).

Abstract: A system, method, and computer program product for improving circuit reliability via circuit schematic simulation. A circuit simulator may netlist and simulate a schematic with a reference stimulus and determine whether a circuit component is a candidate for stress analysis, and store candidate component circuit conditions. A stress test simulation may determine if candidate components are stressed by exposure to simulated conditions meeting a stress test criterion, and output information regarding stressed circuit components. Embodiments may simulate analog integrated circuitry, determine MOS component gate oxide layer area according to component length and width, and monitor conditions on components deemed most likely to be defective, including larger MOS components. A circuit simulator plug-in may avoid storing simulation output waveforms or performing layout based analysis.

Abstract: A method identifying an element in a document corresponding to an edit selected from a list of available edits to distinguish the selected edit from the other edits in the list. The identifying may reflect the type of edit, or otherwise demonstrate the change to the element effectuated by the edit. Multiple edits may be selected and temporarily highlighted or otherwise identified in chronological order to demonstrate the effect of multiple edits on the elements of the document.

Abstract: Various embodiments implement electronic designs with cloning techniques by identifying a root device corresponding to a master design in an electronic design, performing one or more sets of searches for device correspondence with respect to the root device, and implementing the electronic design by at least characterizing the device correspondence based at least in part upon one or more criterion for the one or more sets of searches. These techniques implement the electronic design by characterizing the device correspondence through at least determining whether the device correspondence represents a clone, a mutant, or a user clone and by identifying and replicating clones, mutants, and/or user clones in the electronic design.

Abstract: In a system and method that simulates a design including a third party IP component, a driver for the IP component is compiled and executed in a workstation implementing the simulation platform for the design. The source code for the driver is modified to allow the simulation to reroute certain functions that would cause the simulator to hang until an event occurs that would unlock the simulation. The rerouting includes storing instruction location, state information, and any other context information needed to restore a paused function. The saved information is stored in a stack that is traversed upon detection of the event.

Abstract: Embodiments provide methods, systems, and devices involving transaction correlation tools that may record a limited number of run attributes yet are likely to be important in the debugging process. Some embodiments may include novel tabular representations of the runs. Embodiments may allow the user to specify directives for the recording of the runs and the creation of these tables. Embodiments may include comparing sets of failing and passing runs, which may be generated at random. This approach is called statistical debugging, as it employs statistical tools to find attributes of the DVE that tend to co-occur with the failure.

Abstract: The present disclosure relates to a computer-implemented method for visualization in an electronic design. The method may include providing an electronic design and receiving a selection of at least one pin associated with the electronic design at a first graphical user interface. The method may further include generating a stub for each of the selected pins at the first graphical user interface. The method may also include providing a second graphical user interface configured to allow for the assignment of a signal name to each stub. The method may include extending the stub for each of the selected pins to reach a target destination associated with the electronic design. The method may also include displaying the signal name for each stub on at least one of the first graphical user interface and the second graphical user interface.

Abstract: The present disclosure relates to a computer-implemented method for routing in an electronic circuit design. The method may include assigning a plurality of rats interconnecting one or more terminals associated with a layout of the electronic circuit design to a bundle. The method may further include sequencing the plurality of rats within the assigned bundle to generate a defined sequence of rats within the assigned bundle. The method may also include routing the plurality of rats between the one or more terminals, based upon, at least in part, the defined sequence.

Abstract: A system and method are provided for offloaded lateral transmission between protocol interface devices in an electronic system. Such offloading allows the lateral transmission of data and/or instructions between disparate protocol interface devices without burdening the electronic system's resources, such as the primary processor, memory, and/or system bus. A lateral communication controller is provided to intercouple the first and second protocol interface devices and selectively intercept data packets from one device to be injected into another.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing an electronic design including, at least in part, one or more hardware description languages and one or more software programming languages. Embodiment may also include calculating, using one or more processors, configuration information without analyzing the electronic design, wherein the configuration information includes one or more memory elements configured to control a mode of operation of the electronic design. Embodiments may further include storing a seed for each configuration, wherein each seed may be configured to cause a constraint solver to set a defined set of values for one or more random variables in a class associated with the seed.

Abstract: Systems and methods for creating and placing custom guard rings create a guard ring from a plurality of unit cells reflecting the devices that are enclosed in the guard ring. Using a unit cell identified by a design tool user as the basic unit of the guard ring, with a few additional setup parameters, a complete, content-aware guard ring is created. The guard ring will consist of a collection of the identified unit cells placed around the circuit devices that are to be protected. The created guard ring will function as a single circuit component. Edits to the dimensions and/or parameters of the unit cell will affect the placement of the unit cell in the protected area and will therefore require creation of a new guard ring consistent with the changed parameters.