Patents Assigned to Cadence Design Systems, Inc.
  • Patent number: 9071193
    Abstract: A system and method are provided for augmenting frequency tuning resolution in an L-C oscillatory circuit which comprises a source of electrical energy, and a tuned section energized by said source of electrical energy for oscillatory conduction of a resonant current therethrough. The tuned section includes an inductor portion extending in substantially looped manner between first and second connection points to define at least one turn. A primary capacitor portion is connected across at least a primary segment of the conductive member delineated by the first and second connection points. The tuned section further includes a secondary capacitor portion connected across a secondary segment of the conductive member intermediately tapped from the primary segment.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: June 30, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Anthony Caviglia, Eric H. Naviasky, Hugh Thompson
  • Patent number: 9071238
    Abstract: The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: June 30, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventor: Radu Zlatanovici
  • Patent number: 9069918
    Abstract: A system and method for writing simulation acceleration data from a host workstation to a hardware emulation system without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus and an emulator chip, the emulator chip includes: an emulation processor that generates emulation data, and a data array connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein simulation acceleration data from the host workstation are written to the data array of the emulator chip using the system bus.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: June 30, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell Poplack, Beshara Elmufdi
  • Patent number: 9064063
    Abstract: Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: June 23, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Yu, Joshua Baudhuin, Regis Colwell, Harsh Deshmane, Elias L. Fallon, Sanjib Ghosh, Anjna Khanna, Yinnie Lee, Harindranath Parameswaran, Pardeep Juneja, Roland Ruehl, Simon Simonian, Hui Xu, Timothy Rosek
  • Patent number: 9058440
    Abstract: Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic circuits with specialized power management requirements, such as low power designs. Some approaches provide an improved method and system for providing a highly reliable, usable and scalable solution to allow for designers to use their power information files in a mixed-signal simulation and carry the impact of power intents defined on the digital blocks onto the analog blocks without needing any manual changes to models/designs.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: June 16, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventor: Abhijeet Kolpekwar
  • Patent number: 9053259
    Abstract: Some embodiments correlate various manufacturing or design information or data with patterns used to represent electronic designs and provide pertinent pattern-based information to metrology, fabrication, or testing tools to enhance their performances of their intended functions. Some embodiments further utilize cross-design or cross-process analytics to perform various pattern-based analysis on electronic designs. Some embodiments perform squish analysis with a squish pattern library on an electronic design to represent the electronic design with squish patterns by performing pattern matching, pattern decomposition, and pattern classification process.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 9, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Frank E. Gennari, Matthew Moskewicz, Ya-Chieh Lai
  • Patent number: 9053289
    Abstract: Disclosed is a method and system for visualizing legal locations of edges and dimensions for an object being placed or edited in the layout. During the design process, visual indicators may be provided to the user to indicate the legal locations at which edges of an object may be placed in the layout. Gravitation and/or snapping may be provided automatically identify and/or move the edges to the legal locations. However, the user can control whether and under what circumstances the gravitation and/or snapping will occur. In this way, the designer does not need to manually place the edges of every single object, which is especially helpful for objects that are intended to have an edge at a legal location. Upon a design choice by the designer, the objects can be edited so that an edge does not need to immediately comply with a design rule.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: June 9, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gilles S. C. Lamant, Henry Yu, Simon Simonian, Johannes Franz Xaver Grad, Jeff Taraldson
  • Patent number: 9053270
    Abstract: Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: June 9, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sushobhit Singh, Amit Kumar, Oleg Levitsky
  • Patent number: 9047424
    Abstract: A system, method, and computer program product for automatically providing circuit designers with verification information for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to enter verification IP while simultaneously viewing the design IP in a schematic and/or layout editor window. Embodiments maintain the verification IP in a cellview similar to the separate cellviews used for schematic and layout data. Verification IP may be selectively translated into data that is directly exportable to and usable by particular analog and mixed-signal simulators. Embodiments direct design IP and verification IP to a simulator that dynamically stitches both together during circuit verification, and tangibly outputs verification results.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: June 2, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mark Baker, Donald J. O'Riordan, Keith Dennison
  • Patent number: 9047427
    Abstract: An improved approach for designing and verifying electronic designs at different levels of abstractions is disclosed. An electronic design undergoes high level verification, where the results of the high level verification can be guaranteed to be correct at the RTL level. This can be implemented by ensuring that model consistency rules are followed to generate high level (enhanced transaction level) models and/or RTL data. In this way, properties that are verified at one level of abstraction will not need to be re-verified at the other level of abstraction.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: June 2, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Frederic Doucet, Robert P. Kurshan
  • Patent number: 9043742
    Abstract: Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first hierarchical level from a second force model at the second hierarchical level by directly modifying the second model based at least in part on characteristic(s) of the first hierarchical level and of the second hierarchical level. In a design with multiple hierarchies, a cell-based force model is also used to ensure child nodes of a parent cell stay within a close proximity of the parent node of the parent cell.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 26, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventor: Thaddeus C. McCracken
  • Patent number: 9043771
    Abstract: In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational loop in response to analyzing the computational loop to determine independence of the computational transactions of the computational loop. Multiple instances of the modified application program are executed to provide multi-processing and/or distributed parallel processing.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: May 26, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Harsh Vardhan, Athanasius W. Spyrou
  • Patent number: 9043735
    Abstract: In one embodiment of the invention, an integrated circuit (IC) design tool is provided for synthesizing logic, including one or more software modules to synthesize a gate-level netlist of a squarer functional block. The software modules include a bitvector generator, a bitvector reducer, and a hybrid multibit adder generator. The bitvector generator multiplies bits of a vector together to generate partial products for a plurality of bitvectors and then optimizes a plurality of least significant bitvectors. The bitvector reducer reduces the partial products in the bitvectors of the squarer functional block down to a pair of final vectors. The hybrid multibit adder generator generates a hybrid multibit adder including a first adder and a second adder coupled together by a carry bit with bit widths being responsive to a dividerbit. The hybrid multibit adder adds the pair of final vectors together to generate a final result for the squarer functional block.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: May 26, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sabyasachi Das, Jean-Charles Giomi
  • Patent number: 9038002
    Abstract: A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: May 19, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventor: Vishnu Govind Kamat
  • Patent number: 9038008
    Abstract: A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 19, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Jaideep Mukherjee, Richard J. O'Donovan
  • Patent number: 9032347
    Abstract: A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: May 12, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventor: Donald J. O'Riordan
  • Patent number: 9026960
    Abstract: The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some embodiment, in addition to viewing a floorplan, further comprise of modifying the floorplan. Furthermore, some embodiments provide a method that further comprises fixing the violations that result from the lithography analysis.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 5, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chayan Majumder, Pawan Fangaria
  • Patent number: 9026966
    Abstract: The present patent document relates to a method and apparatus for more efficiently simulating a circuit design (DUT), making use of a hardware functional verification device such as a processor-based emulator. A set of linked databases are compiled for the DUT, one for hardware emulation (without timing information for the DUT) and one for software simulation (including timing information) that remain synchronized during runtime. The compiled design is run in a hardware emulator during an initialization/configuration phase and the state saved. The state is then swapped to a software simulator where timing information, such as SDF timing, may be honored during the second part of the run and the user's test bench stimuli applied to the design.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: May 5, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Naresh Ramachandran, G. B. Ashok, Ping-Sheng Tseng
  • Patent number: 9026958
    Abstract: Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple edges and multiple nodes. The method, system and computer product further include detecting all possible odd loops in each of the plurality of sub-graphs; and visualizing all of the odd loops in at least one of the plurality of sub-graphs.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 5, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sanjib Ghosh, Harindranath Parameswaran, Henry Yu
  • Patent number: 9026978
    Abstract: A system, method, and computer program product for automatically optimizing circuit designs. A graphical user interface based environment allows arbitrary selection of a circuit design region to be optimized based on physical layout, without regard for logical hierarchy. Embodiments analyze circuit paths crossing optimization region boundaries and replace externally connected circuitry with an interface logic model describing such circuitry from the optimization region boundary to a first register occurrence. A reduced netlist spans the regional circuitry and the modeled external circuitry. Embodiments optimize the reduced netlist under design constraints applicable to the full circuit design. Changes to the original circuit design made by the optimization are tangibly saved as engineering change orders. The optimization process may be applied to other regions, including via parallel execution by multiple processors.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: May 5, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Dongzi Liu, Yi Qian, Wanshuan Liu, Pinhong Chen, WenHsing Tsai, Yanhui Wang