Abstract: A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

Abstract: Various embodiments describe methods and systems for dynamic IP protection in electronic circuit designs. The methods or systems determine one or more levels of access or encryption and identify design data that should be made available for each level. For each level, a pcell instance is created to hide actual design data, and the design data that should be made available are moved to an instance of the corresponding sub-master in memory. The design data in this instance are encrypted in memory and are persisted in a side file in a non-volatile computer accessible storage medium. An authorized user is provided with a key, the side file, and a decrypting scheme to retrieve the actual design data with an appropriate level of details from the side file during a pcell evaluation process.

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.

Abstract: A multimode physical (MMP) layer circuit for physical (PHY) layer handling of signals transported over a high-definition multimedia interface (HDMI) cable in a home multimedia network, wherein the signals are compliant with at least two different PHY layer modes. The MMP layer circuits comprises a plurality of PHY transceivers respectively coupled to a plurality of TP channels of the HDMI cable through a HDMI connector, wherein each PHY transceiver of the plurality of PHY transceivers handles signals transported over its respective TP channel according to a PHY layer mode of the transported signals; and a controller is coupled to the HDMI connector and to each of the plurality of PHY transceivers, the controller recognizes the PHY layer mode of signals transported over each of the plurality of TP channels and sets each of the plurality of PHY transceivers according to the recognized PHY layer mode.

Abstract: Technology for finite-state machine (FSM) encoding during design synthesis for a circuit is disclosed. The encoding of the FSM may include determining values of a multi-bit state register that are to represent particular states of the FSM. These values may be determined based on possible states of the FSM, possible transitions between the states, probabilities of particular transitions occurring, amounts of false switching associated with particular transitions, area estimates for logic respectively associated with states of the FSM, and/or the like. The values may also be determined based on power considerations, such as estimated power consumption for the circuit. The design synthesis may include generation of a structural description of the encoded FSM.

Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Abstract: A method and apparatus for redundant communication channels in an emulation system is disclosed. A processor-based emulation system has a plurality of emulation chips on an emulation board. The emulation chips have a plurality of processor clusters. Signals are sent over one or more communication channels between processor clusters, including from a processor cluster on one emulation chip to a processor cluster on another emulation chip. Copies of the same signal may be sent in duplicate over separate communication channels. If a communication channel failure is detected, instruction memory is modified so that a processor cluster's instructions no longer address a first cluster memory location, but instead address a second cluster memory location of a non-failed communication channel. By using redundant communication channels, emulation system interconnect reliability is increased and recompilation of the design under verification may be avoided.

Abstract: A system and method are provided for the detection and correction of metastability errors in a successive approximation analog to digital converter (ADC). The successive approximation ADC (40) includes a comparator unit (424) that includes a NAND gate circuit (550) that outputs a comp_rdy_n signal when the comparator (500) has latched a result. ADC (40) includes a metastability detection and correction circuit (425) that includes a first logic circuit (700) that monitors the comp_rdy_n signal and detects a metastable event if that signal is not received within a portion of a conversion time period of the ADC. Responsive to detection of a metastable event, a second logic circuit (750) generates a correct conversion code at the output of the ADC. If no metastable event is detected during a conversion cycle of the ADC, the second logic circuit (750) outputs the conversion codes determined by the comparator (500).

Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute. Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition. Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration. Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations.

Abstract: A netlist description that includes embedded code segments for describing a circuit is preprocessed in order to replace the embedded code segments with corresponding preprocessed code segments, where the preprocessed code segments include netlist code that can be parsed and executed. To perform this preprocessing, programming languages that include scripting operations are identified for the embedded code segments in the netlist description. A pipeline preprocessor that includes preprocessors for the identified programming languages is configured to sequentially process the netlist description and replace the embedded code segments with the corresponding preprocessed code segments.

Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. When the samples exceed the mismatch parameters, a linear model is solved by least squares. Otherwise, a linear model is solved by orthogonal matching pursuit (OMP), and if that solution is too inaccurate then a new mixed method builds a better linear model. If the linear solution is too inaccurate, a full linear and quadratic model is made using OMP to select the most important variables, and the full model is fitted using OMP with selected cross terms. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions.

Abstract: In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.

Abstract: A system, method, and computer program product is disclosed for performing electrical analysis of a circuit design. A voltage-based approach is described for performing two-stage transient EM-IR drop analysis of an electronic design. A two-stage approach is performed in some embodiments, in which the first stage operates by calculating the voltage at certain interface nodes. In the second stage, simulation is performed to simulate the circuit to concurrently obtain the current at the interface nodes. In some embodiments, multiple adjacent devices as identified as interface devices for purposes of the analysis. One situation where it may be useful to analyze a larger portion of the circuitry in this way where the analysis is being performed on a netlist having a power gate.

Abstract: In a circuit simulation tool in a computer system having one or more computer processors and computer-readable storage, a method for characterizing a driven oscillator circuit having an oscillator coupled to a time-varying input signal includes retrieving information provided in a circuit description of the oscillator circuit. The method also includes forming a frequency-domain harmonic balance equation for the oscillator circuit using the retrieved information provided in the circuit description of the oscillator circuit. The harmonic balance equation includes a first differential operator in a frequency domain of the input signal and a product of a differential operator in a second frequency domain of the oscillator and a frequency variable of the oscillator. The frequency variable is independent of the frequency domain of the input signal. The method further includes solving the harmonic balance equation to obtain a waveform description of the oscillator circuit.

Abstract: Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.

Abstract: Some embodiments of the invention provide a method for balancing the assignment of shapes from a portion of an IC design layout to different masks. The method of some embodiments assigns the shapes to a plurality of masks in a manner that a variation between the numbers of shapes assigned to each mask is within a certain threshold. The method of some embodiments performs a separate analysis for shapes which are outside of a threshold distance from any other shapes.

Abstract: Method and system for verifying data in a database. In one aspect, verifying data includes receiving an indication of at least one policy, the at least one policy including at least one rule. A verification process is initiated on target data by implementing the at least one policy, where implementing the at least one policy includes instantiating and applying the at least one rule. The at least one rule causes at least one verification check to be performed on the target data.

Abstract: A multimedia interface cable for achieving complete interoperability between different types of multimedia display interfaces. The cable comprises a first multimedia connector including a plurality of contact pins of at least high-speed multimedia signals and control signals; a second multimedia connector including a plurality of contact pins of least high-speed multimedia signals and control signals; a plurality of un-crossing conducting wires for coupling the plurality of contact pins of the high-speed multimedia signals in the first multimedia connector to the plurality of contact pins of the high-speed multimedia signals in the second multimedia connector; and a plurality of conducting wires for coupling the plurality of contact pins of the control signals in the first multimedia connector to the plurality of contact pins of the control signals in the second multimedia connector.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. The method may include providing, using a processor, a low-power electronic design and determining if a power domain associated with the low-power electronic design is active. The method may further include identifying, at a register transfer level (RTL) at least one X value associated with an active power domain wherein identifying occurs during a simulation.

Abstract: The present disclosure relates to a computer-implemented method for simulating an analog and mixed-signal circuit design having a digital circuit segment connected to an analog circuit segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the digital circuit segment and the analog circuit segment. The method may further include splitting the digital circuit segment into a plurality of transistor network models to provide for bidirectional transfer of data between the analog circuit segment and the digital circuit segment.